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[plat] add t113 support and bard 100ask-t113s3
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set(APP_COMMON_SOURCE | ||
${CMAKE_CURRENT_SOURCE_DIR}/start.S | ||
${CMAKE_CURRENT_SOURCE_DIR}/board.c | ||
${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c | ||
) | ||
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add_subdirectory(hello_world) |
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# SyterKit Common | ||
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## start.S | ||
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This code snippet is an ARM assembly language program that includes initialization settings and exception handlers. Here's a breakdown of its functionalities: | ||
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1. Initialization Settings: It sets registers and writes specific values to configure the processor's working mode, interrupt enable, etc. | ||
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2. Set Vector Table: It writes the address of the vector table to the Vector Base Address Register, which is used for handling exceptions and interrupts. | ||
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3. Enable NEON/VFP Unit: It configures the processor to enable the NEON (Advanced SIMD) and VFP (Floating-Point) units. | ||
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4. Clear BSS Section: It zeroes out variables in the BSS section. | ||
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5. Disable Interrupts: It disables FIQ and IRQ interrupts and switches the processor to SVC32 mode. | ||
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6. Set Timer Frequency: It sets the timer frequency to 24M. | ||
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7. Call the main Function: It jumps to the main function to execute the main logic. | ||
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## eabi_compat.c | ||
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This code snippet appears to be providing implementations for the functions `abort`, `raise`, and `__aeabi_unwind_cpp_pr0`. Here's a breakdown of their functionalities: | ||
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1. `void abort(void)`: This function creates an infinite loop, causing the program to hang indefinitely. It is typically used to indicate a critical error or unrecoverable condition in a program. | ||
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2. `int raise(int signum)`: This function is a placeholder and always returns 0. In standard C, this function is used to raise a signal and initiate the corresponding signal handler. However, in this implementation, it does nothing and simply returns 0. | ||
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3. `void __aeabi_unwind_cpp_pr0(void)`: This is a dummy function that serves as a placeholder to avoid linker complaints. Its purpose is to satisfy the linker when using C++ exceptions and unwinding, but it does not contain any actual functionality. |
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#include <stdbool.h> | ||
#include <stddef.h> | ||
#include <stdint.h> | ||
#include <types.h> | ||
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#include <log.h> | ||
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#include <common.h> | ||
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#include <sys-clk.h> | ||
#include <reg-ncat.h> | ||
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#include <mmu.h> | ||
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#include <sys-gpio.h> | ||
#include <sys-spi.h> | ||
#include <sys-uart.h> | ||
#include <sys-sdcard.h> | ||
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sunxi_serial_t uart_dbg = { | ||
.base = 0x02500000, | ||
.id = 0, | ||
.gpio_tx = {GPIO_PIN(GPIO_PORTE, 2), GPIO_PERIPH_MUX5}, | ||
.gpio_rx = {GPIO_PIN(GPIO_PORTE, 3), GPIO_PERIPH_MUX5}, | ||
}; | ||
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sunxi_spi_t sunxi_spi0 = { | ||
.base = 0x04025000, | ||
.id = 0, | ||
.clk_rate = 75 * 1000 * 1000, | ||
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4}, | ||
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4}, | ||
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4}, | ||
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4}, | ||
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4}, | ||
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4}, | ||
}; | ||
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sdhci_t sdhci0 = { | ||
.name = "sdhci0", | ||
.reg = (sdhci_reg_t *) 0x04020000, | ||
.voltage = MMC_VDD_27_36, | ||
.width = MMC_BUS_WIDTH_4, | ||
.clock = MMC_CLK_50M, | ||
.removable = 0, | ||
.isspi = FALSE, | ||
.gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2}, | ||
.gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2}, | ||
.gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2}, | ||
.gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2}, | ||
.gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2}, | ||
.gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2}, | ||
}; | ||
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void clean_syterkit_data(void) { | ||
/* Disable MMU, data cache, instruction cache, interrupts */ | ||
arm32_mmu_disable(); | ||
printk(LOG_LEVEL_INFO, "disable mmu ok...\n"); | ||
arm32_dcache_disable(); | ||
printk(LOG_LEVEL_INFO, "disable dcache ok...\n"); | ||
arm32_icache_disable(); | ||
printk(LOG_LEVEL_INFO, "disable icache ok...\n"); | ||
arm32_interrupt_disable(); | ||
printk(LOG_LEVEL_INFO, "free interrupt ok...\n"); | ||
} |
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/* SPDX-License-Identifier: Apache-2.0 */ | ||
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void abort(void) { | ||
while (1) | ||
; | ||
} | ||
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int raise(int signum) { | ||
return 0; | ||
} | ||
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/* Dummy function to avoid linker complaints */ | ||
void __aeabi_unwind_cpp_pr0(void) { | ||
} |
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# SPDX-License-Identifier: Apache-2.0 | ||
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add_syterkit_app(helloworld | ||
main.c | ||
) |
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/* SPDX-License-Identifier: Apache-2.0 */ | ||
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#include <stdbool.h> | ||
#include <stddef.h> | ||
#include <stdint.h> | ||
#include <types.h> | ||
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#include <log.h> | ||
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extern sunxi_serial_t uart_dbg; | ||
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int main(void) { | ||
sunxi_serial_init(&uart_dbg); | ||
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sunxi_clk_init(); | ||
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printk(LOG_LEVEL_INFO, "Hello World!\n"); | ||
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return 0; | ||
} |
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/* SPDX-License-Identifier: Apache-2.0 */ | ||
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#include <linkage.h> | ||
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#define ARMV7_USR_MODE 0x10 | ||
#define ARMV7_FIQ_MODE 0x11 | ||
#define ARMV7_IRQ_MODE 0x12 | ||
#define ARMV7_SVC_MODE 0x13 | ||
#define ARMV7_MON_MODE 0x16 | ||
#define ARMV7_ABT_MODE 0x17 | ||
#define ARMV7_UND_MODE 0x1b | ||
#define ARMV7_SYSTEM_MODE 0x1f | ||
#define ARMV7_MODE_MASK 0x1f | ||
#define ARMV7_FIQ_MASK 0x40 | ||
#define ARMV7_IRQ_MASK 0x80 | ||
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.arm | ||
.globl reset | ||
.text | ||
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reset: | ||
/* Boot head information for BROM */ | ||
.long 0xea000016 | ||
.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0' | ||
.long 0x12345678 /* checksum */ | ||
.long __spl_size /* spl size */ | ||
.long 0x30 /* boot header size */ | ||
.long 0x30303033 /* boot header version */ | ||
.long 0x00020000 /* return value */ | ||
.long 0x00028000 /* run address */ | ||
.long 0x0 /* eGON version */ | ||
.byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */ | ||
.byte 0x34, 0x2e, 0x30, 0x00 | ||
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/* | ||
* The actual reset code | ||
*/ | ||
mrs r0, cpsr | ||
bic r0, r0, #ARMV7_MODE_MASK | ||
orr r0, r0, #ARMV7_SVC_MODE | ||
orr r0, r0, #(ARMV7_IRQ_MASK | ARMV7_FIQ_MASK) | ||
bic r0, r0, #(1<<9) @set little-endian | ||
msr cpsr_c, r0 | ||
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/* Set vector base address register */ | ||
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ldr r0, =_vector | ||
mcr p15, 0, r0, c12, c0, 0 | ||
mrc p15, 0, r0, c1, c0, 0 | ||
bic r0, #(1 << 13) | ||
mcr p15, 0, r0, c1, c0, 0 | ||
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mrc p15, 0, r0, c1, c0, 0 | ||
bic r0, r0, #0x00002000 @ clear bits 13 (--V-) | ||
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) | ||
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB | ||
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache | ||
mcr p15, 0, r0, c1, c0, 0 | ||
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/* Enable neon/vfp unit */ | ||
mrc p15, 0, r0, c1, c0, 2 | ||
orr r0, r0, #(0xf << 20) | ||
mcr p15, 0, r0, c1, c0, 2 | ||
isb | ||
mov r0, #0x40000000 | ||
vmsr fpexc, r0 | ||
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/* Set stack pointer */ | ||
ldr sp, =__stack_srv_end | ||
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bl clear_bss | ||
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/* | ||
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, | ||
* except if in HYP mode already | ||
*/ | ||
mrs r0, cpsr | ||
and r1, r0, #0x1f @ mask mode bits | ||
teq r1, #0x1a @ test for HYP mode | ||
bicne r0, r0, #0x1f @ clear all mode bits | ||
orrne r0, r0, #0x13 @ set SVC mode | ||
orr r0, r0, #0xc0 @ disable FIQ and IRQ | ||
msr cpsr,r0 | ||
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@set cntfrq to 24M | ||
ldr r0, =24000000 | ||
mcr p15, 0, r0, c14, c0, 0 | ||
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bl set_timer_count | ||
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bl main | ||
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clear_bss: | ||
ldr r0, =_sbss | ||
ldr r1, =_ebss | ||
mov r2, #0 | ||
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clbss_1: | ||
stmia r0!, {r2} | ||
cmp r0, r1 | ||
blt clbss_1 | ||
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mov pc, lr | ||
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_vector: | ||
b reset | ||
ldr pc, _undefined_instruction | ||
ldr pc, _software_interrupt | ||
ldr pc, _prefetch_abort | ||
ldr pc, _data_abort | ||
ldr pc, _not_used | ||
ldr pc, _irq | ||
ldr pc, _fiq | ||
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_undefined_instruction: | ||
.word undefined_instruction | ||
_software_interrupt: | ||
.word software_interrupt | ||
_prefetch_abort: | ||
.word prefetch_abort | ||
_data_abort: | ||
.word data_abort | ||
_not_used: | ||
.word not_used | ||
_irq: | ||
.word irq | ||
_fiq: | ||
.word fiq | ||
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.macro save_regs | ||
str lr, [sp, #-4] | ||
mrs lr, spsr_all | ||
str lr, [sp, #-8] | ||
str r1, [sp, #-12] | ||
str r0, [sp, #-16] | ||
mov r0, sp | ||
cps #0x13 | ||
ldr r1, [r0, #-4] | ||
str r1, [sp, #-4]! | ||
ldr r1, [r0, #-8] | ||
str r1, [sp, #-(4 * 16)] | ||
ldr r1, [r0, #-12] | ||
ldr r0, [r0, #-16] | ||
stmdb sp, {r0 - r14}^ | ||
sub sp, sp, #(4 * 16) | ||
ldr r4, [sp] | ||
and r0, r4, #0x1f | ||
cmp r0, #0x10 | ||
beq 10f | ||
cmp r0, #0x13 | ||
beq 11f | ||
b . | ||
11: add r1, sp, #(4 * 17) | ||
str r1, [sp, #(4 * 14)] | ||
str lr, [sp, #(4 * 15)] | ||
10: add r1, sp, #(4 * 17) | ||
str r1, [sp, #-4]! | ||
mov r0, sp | ||
.endm | ||
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.macro restore_regs | ||
mov r12, sp | ||
ldr sp, [r12], #4 | ||
ldr r1, [r12], #4 | ||
msr spsr_cxsf, r1 | ||
and r0, r1, #0x1f | ||
cmp r0, #0x10 | ||
beq 20f | ||
cmp r0, #0x13 | ||
beq 21f | ||
b . | ||
20: ldr lr, [r12, #(4 * 15)] | ||
ldmia r12, {r0 - r14}^ | ||
movs pc, lr | ||
21: ldm r12, {r0 - r15}^ | ||
mov r0, r0 | ||
.endm | ||
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/* | ||
* Exception handlers | ||
*/ | ||
.align 5 | ||
undefined_instruction: | ||
sub lr, lr, #4 | ||
save_regs | ||
bl arm32_do_undefined_instruction | ||
restore_regs | ||
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.align 5 | ||
software_interrupt: | ||
sub lr, lr, #4 | ||
save_regs | ||
bl arm32_do_software_interrupt | ||
restore_regs | ||
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.align 5 | ||
prefetch_abort: | ||
sub lr, lr, #4 | ||
save_regs | ||
bl arm32_do_prefetch_abort | ||
restore_regs | ||
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.align 5 | ||
data_abort: | ||
sub lr, lr, #8 | ||
save_regs | ||
bl arm32_do_data_abort | ||
restore_regs | ||
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.align 5 | ||
not_used: | ||
b . | ||
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.align 5 | ||
irq: | ||
sub lr, lr, #4 | ||
save_regs | ||
bl arm32_do_irq | ||
restore_regs | ||
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.align 5 | ||
fiq: | ||
sub lr, lr, #4 | ||
save_regs | ||
bl arm32_do_fiq | ||
restore_regs |
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