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i3c_controller: clean-up, add debug parameter
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Invert speed grade values order.
Remove clk_div module.
Add DEBUG_IGNORE_NACK parameter to ignore when a transfer is NACKed,
useful for testing without a peripheral on the bus,

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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@gastmaier
gastmaier committed Oct 17, 2023
1 parent cc25bbe commit a0c5e92
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Showing 6 changed files with 55 additions and 134 deletions.
14 changes: 8 additions & 6 deletions docs/regmap/adi_regmap_i3c_controller.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -421,14 +421,14 @@ ENDREG
FIELD
[0] 0x??
OPS_MODE
WO
RW
Set 0 to private transfers, 1 to offload.
ENDFIELD

FIELD
[4:1] 0x??
OPS_OFFLOAD_LENGTH
WO
RW
Offload commands length.
ENDFIELD

Expand All @@ -438,10 +438,10 @@ OPS_SPEED_GRADE
RW
Sets the speed grade in push-pull mode.
Speed with 100MHz driver clock are:
00: 12.50MHz
01: 6.25MHz
10: 3.12MHz
11: 1.56MHz (default)
00: 1.56MHz (default)
01: 3.12MHz
10: 6.25MHz
11: 12.50MHz
ENDFIELD

[5] 0x0
Expand Down Expand Up @@ -595,6 +595,8 @@ The state can also be overwritten to explicit attach device (e.g. has static add
A slot cannot be recycled, when the device is detached, it still keeps its slot in
case it is attached again, effectively, only its IBIs are rejectedin the detached
state.
The controller cannot be detached, instead, poll OPS_STATUS_NOP to identify if the
controller is doing free/not doing any procedure before recondiguring it.
ENDFIELD

FIELD
Expand Down
20 changes: 10 additions & 10 deletions library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v
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Expand Up @@ -49,10 +49,10 @@ module i3c_controller_bit_mod (
// Indicates that the bus is not transfering,
// is different from bus idle because does not wait 200us after Stop.
output cmd_nop,
// 0: 12.50MHz
// 1: 6.25MHz
// 2: 3.12MHz
// 3: 1.56MHz
// 0: 1.56MHz
// 1: 3.12MHz
// 2: 6.25MHz
// 3: 12.50MHz
input [1:0] scl_pp_sg, // SCL Push-pull speed grade

output rx,
Expand All @@ -75,7 +75,7 @@ module i3c_controller_bit_mod (
reg sr;

reg scl_high_reg;
wire scl_high = count[pp_sg+2];
wire scl_high = count[5-pp_sg];
wire sdo_w;
wire t_w;

Expand All @@ -85,7 +85,7 @@ module i3c_controller_bit_mod (
for (i = 0; i < 4; i = i+1) begin
assign scl_end_multi[i] = &count[i+2:0];
end
assign scl_end = scl_end_multi[pp_sg];
assign scl_end = scl_end_multi[3-pp_sg];

assign cmd_ready = (scl_end | !transfer) & reset_n;

Expand All @@ -95,12 +95,12 @@ module i3c_controller_bit_mod (
always @(posedge clk) begin
if (!reset_n) begin
cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01};
pp_sg <= 2'b11;
pp_sg <= 2'b00;
end else begin
if (cmd_ready) begin
if (cmd_valid) begin
cmd_r <= cmd;
pp_sg <= cmd[1] ? scl_pp_sg : 2'b11;
pp_sg <= cmd[1] ? scl_pp_sg : 2'b00;
end else begin
cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01};
end
Expand Down Expand Up @@ -138,8 +138,8 @@ module i3c_controller_bit_mod (
assign rx = rx_raw;
assign rx_valid = ~scl_high_reg & scl_high;

assign sdo_w = sm == `MOD_BIT_CMD_START_ ? (scl_high ? ~count[pp_sg+1] : 1'b1) :
sm == `MOD_BIT_CMD_STOP_ ? (scl_high ? count[pp_sg+1] : 1'b0) :
assign sdo_w = sm == `MOD_BIT_CMD_START_ ? (scl_high ? ~count[4-pp_sg] : 1'b1) :
sm == `MOD_BIT_CMD_STOP_ ? (scl_high ? count[4-pp_sg] : 1'b0) :
sm == `MOD_BIT_CMD_WRITE_ ? st[0] :
sm == `MOD_BIT_CMD_ACK_SDR_ ? (scl_high ? rx : 1'b1) :
sm == `MOD_BIT_CMD_ACK_IBI_ ? (scl_high ? 1'b1 : 1'b0) :
Expand Down
80 changes: 0 additions & 80 deletions library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v
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This file was deleted.

1 change: 0 additions & 1 deletion library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl
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Expand Up @@ -12,7 +12,6 @@ ad_ip_files i3c_controller_core [list \
i3c_controller_word_cmd.v \
i3c_controller_bit_mod.v \
i3c_controller_bit_mod_cmd.v \
i3c_controller_clk_div.v \
]

# parameters
Expand Down
1 change: 0 additions & 1 deletion library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl
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Expand Up @@ -11,7 +11,6 @@ adi_ip_files i3c_controller_core [list \
"i3c_controller_word_cmd.v" \
"i3c_controller_bit_mod.v" \
"i3c_controller_bit_mod_cmd.v" \
"i3c_controller_clk_div.v" \
]

adi_ip_properties_lite i3c_controller_core
Expand Down
73 changes: 37 additions & 36 deletions library/i3c_controller/i3c_controller_core/i3c_controller_word.v
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Expand Up @@ -38,47 +38,49 @@
*/

`timescale 1ns/100ps
`default_nettype none
`default_nettype wire
`include "i3c_controller_word_cmd.v"
`include "i3c_controller_bit_mod_cmd.v"

module i3c_controller_word (
input wire clk,
input wire reset_n,
module i3c_controller_word #(
parameter DEBUG_IGNORE_NACK = 0
) (
input clk,
input reset_n,

// Word command

output reg cmdw_nack,
// NACK is HIGH when an ACK is not satisfied in the I3C bus, acts as reset.
output wire cmdw_ready,
input wire cmdw_valid,
input wire [`CMDW_HEADER_WIDTH+8:0] cmdw,
output cmdw_ready,
input cmdw_valid,
input [`CMDW_HEADER_WIDTH+8:0] cmdw,

input wire cmdw_rx_ready,
output reg cmdw_rx_valid,
output wire [7:0] cmdw_rx,
input cmdw_rx_ready,
output reg cmdw_rx_valid,
output [7:0] cmdw_rx,

// Bit Modulation Command

output wire [`MOD_BIT_CMD_WIDTH:0] cmd,
output wire cmd_valid,
input wire cmd_ready,
output [`MOD_BIT_CMD_WIDTH:0] cmd,
output cmd_valid,
input cmd_ready,

// RX and ACK

input wire rx,
input wire rx_valid,
input rx,
input rx_valid,

// IBI interface

output reg arbitration_valid,
input wire ibi_bcr_2,
output reg ibi_requested,
input wire ibi_requested_auto,
output reg ibi_tick,
output wire [6:0] ibi_da,
input wire ibi_da_attached,
output wire [7:0] ibi_mdb,
output reg arbitration_valid,
input ibi_bcr_2,
output reg ibi_requested,
input ibi_requested_auto,
output reg ibi_tick,
output [6:0] ibi_da,
input ibi_da_attached,
output [7:0] ibi_mdb,

// DAA interface

Expand All @@ -87,10 +89,9 @@ module i3c_controller_word (

// uP accessible info

input wire [1:0] rmap_ibi_config
input [1:0] rmap_ibi_config
);
wire ibi_enable;
wire ibi_auto;

wire [`CMDW_HEADER_WIDTH:0] cmdw_header;

Expand All @@ -107,14 +108,11 @@ module i3c_controller_word (

reg do_ack; // Peripheral did NACK?
reg do_rx_t; // Peripheral end Message at T in Read Data?
reg rx_sampled;
reg sg;
reg [`MOD_BIT_CMD_WIDTH:2] cmd_r;
reg cmd_wr;

reg [5:0] i;
reg [5:0] i_reg;
reg [5:0] i_reg_2;
reg [5:0] i_;
// # of Bit Modulation Commands - 1 per word
always @(sm) begin
Expand Down Expand Up @@ -331,13 +329,17 @@ module i3c_controller_word (
`CMDW_TARGET_ADDR_PP,
`CMDW_BCAST_7E_W1,
`CMDW_BCAST_7E_W0: begin
if (do_ack & rx !== 1'b0) begin
sm <= `CMDW_STOP_OD;
smt <= setup;
cmdw_nack <= 1'b1; // Tick
// Due to NACK'ED STOP inheriting NACK'ED word i value,
// this flag makes sm goto get after STOP cmd.
cmdw_nacked <= 1'b1;
// Debug parameter to pretend all ACK bits have been ACKed,
// useful for bus testing without a part.
if (!DEBUG_IGNORE_NACK) begin
if (do_ack & rx !== 1'b0) begin
sm <= `CMDW_STOP_OD;
smt <= setup;
cmdw_nack <= 1'b1; // Tick
// Due to NACK'ED STOP inheriting NACK'ED word i value,
// this flag makes sm goto get after STOP cmd.
cmdw_nacked <= 1'b1;
end
end
end
`CMDW_MSG_RX: begin
Expand Down Expand Up @@ -411,7 +413,6 @@ module i3c_controller_word (
assign ibi_da = ibi_da_reg [8:2];
assign ibi_mdb = ibi_mdb_reg[8:1];
assign ibi_enable = rmap_ibi_config[0];
assign ibi_auto = rmap_ibi_config[1];
assign cmd_valid = smt == transfer;
assign cmd = {cmd_r, sg, cmd_wr};
endmodule

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