SPI Engine: Fixed delay behaviour on Chip-Select and Sleep instructions #1200
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- previously, a sleep time happened before the chip select change - the intended behaviour was for another sleep time, of equal amount, to happen after the chip select change as well - additionally, the counter logic implementation was creating an additional factor of 2 on the sleep time All of the above points were fixed. The changes introduced also fix another issue where the sleep instruction was likewise happening with a duration larger than intended by a factor of 2 Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
… behaviour. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
LBFFilho
requested review from
acostina,
AndreiGrozav and
PopPaul2021
as code owners
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gastmaier
requested changes
Oct 18, 2023
…han 0. Updated delay documentation to match behavior. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
gastmaier
approved these changes
Oct 26, 2023
acostina
approved these changes
Oct 30, 2023
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PR Description
This PR fixes observed behavior of the Chip-Select and Sleep instructions not matching the documentation. A separate testbench was created for this behavior on a fork. A corresponding PR will be created for the testbench. To run it, simply go to the testbenches/pulsar_adc_pmdz directory, and run
make CFG=cfg1 TST=sleep_delay_testAccording to the documentation on the wiki, the Sleep instruction should sleep for
sleep_time = (t + 1) * ((div + 1) * 2) / f_clkwhere "t" is the parameter given to the sleep instruction. However, the current SPI engine implementation (before this PR) actually sleeps for double the duration, due to the way the counter was implemented. The Chip-Select instruction was also affected by this.
The Chip-Select instruction documentation states that the instruction was supposed to create a delay before and after the CS change. The delay after a CS change is useful when implementing fast SPI converters, which sometimes have some timing requirements between CS activation and a SCLK edge. However, the behavior before this PR is that the full delay was happening only before the CS change. Additionally, as stated above, the counter implementation made the delay double (but didn't make it happen after the CS change).
The wiki documentation gives the following for the Chip-Select instruction, where t is the delay parameter:
delay_per_edge = t * (div + 1) / f_clkThis would imply that this instruction does not use the same prescaler as the rest of the SPI Engine, so I updated the formula on the .rst documentation to reflect this, to:
delay_per_edge = t * (div + 1) *2/ f_clkThe changes introduced do not affect the behavior for CS when t=0, which, as far as I know is the common case. So it shouldn't break any existing projects.
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