projects: Port AD9265-FMC to ZedBoard & doc.

docs/projects/ad9265_fmc/index.rst

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+.. _ad9265_fmc:
+
+AD9265-FMC HDL project
+================================================================================
+
+Overview
+-------------------------------------------------------------------------------
+
+The :adi:`AD9265` is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The
+:adi:`AD9265` is designed to support communications applications where high
+performance combined with low cost, small size, and versatility is desired. The
+ADC core features a multistage, differential pipelined architecture with
+integrated output error correction logic to provide 16-bit accuracy at 125 MSPS
+data rates and guarantees no missing codes over the full operating temperature
+range. The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR).
+A data output clock is provided to ensure proper latch timing with receiving
+logic. The board also provides other options to drive the clock and analog
+inputs of the ADC.
+
+Supported boards
+-------------------------------------------------------------------------------
+
+-  :adi:`EVAL-AD9265 <EVAL-AD9265>`
+
+Supported devices
+-------------------------------------------------------------------------------
+
+-  :adi:`AD9265`
+
+Supported carriers
+-------------------------------------------------------------------------------
+
+.. list-table::
+   :widths: 35 35 30
+   :header-rows: 1
+
+   * - Evaluation board
+     - Carrier
+     - FMC slot
+   * - :adi:`EVAL-AD9265-FMC-500EBZ <EVAL-AD9265>`
+     - :xilinx:`ZC706`
+     - FMC LPC
+   * -
+     - :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>`
+     - FMC LPC
+
+Block design
+-------------------------------------------------------------------------------
+
+Block diagram
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. image:: ad9265_fmc_block_diagram.svg
+   :width: 800
+   :align: center
+   :alt: AD9265/ZedBoard block diagram
+
+Clock scheme
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+There are 3 ways to configure the clock source for :adi:`AD9265`:
+
+- External passive clock (default)
+- Optional active clock path using the :adi:`AD9517`
+- Optional oscillator
+
+For more details, check :adi:`AD9265` schematic.
+
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL (see more at :ref:`architecture`).
+
+Check-out the table below to find out the conditions.
+
+==================== ===============
+Instance             Zynq/Microblaze
+==================== ===============
+axi_ad9265           0x44A00000     
+axi_ad9265_dma       0x44A30000     
+==================== ===============
+
+SPI connections
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :widths: 25 25 25 25
+   :header-rows: 1
+
+   * - SPI type
+     - SPI manager instance
+     - SPI subordinate
+     - CS
+   * - PS
+     - SPI 0
+     - AD9517
+     - 1
+
+Interrupts
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Below are the Programmable Logic interrupts used in this project.
+
+.. list-table::
+   :widths: 30 10 15 15
+   :header-rows: 1
+
+   * - Instance name
+     - HDL
+     - Linux Zynq
+     - Actual Zynq
+   * - axi_ad9265_dma
+     - 13
+     - 57
+     - 89
+
+Building the HDL project
+-------------------------------------------------------------------------------
+
+The design is built upon ADI's generic HDL reference design framework.
+ADI distributes the bit/elf files of these projects as part of the
+:dokuwiki:`ADI Kuiper Linux <resources/tools-software/linux-software/kuiper-linux>`.
+If you want to build the sources, ADI makes them available on the
+:git-hdl:`HDL repository </>`. To get the source you must
+`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
+the HDL repository.
+
+Then go to the project location (**projects/ad9265_fmc/carrier**) and run the
+make command by typing in your command prompt(this example :xilinx:`ZC706`):
+
+**Linux/Cygwin/WSL**
+
+.. code-block::
+
+   user@analog:~$ cd hdl/projects/ad9265_fmc/zc706
+   user@analog:~/hdl/projects/ad9265_fmc/zc706$ make
+
+A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
+
+Resources
+-------------------------------------------------------------------------------
+
+Systems related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Here you can find the quick start guides available for these evaluation boards:
+
+.. list-table::
+   :widths: 20 10
+   :header-rows: 1
+
+   * - Evaluation board
+     - Zynq-7000
+   * - AD9265-FMC
+     - :dokuwiki:`ZC706 <resources/fpga/xilinx/fmc/ad9265>`
+
+Hardware related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Product datasheets: :adi:`AD9265`
+-  :dokuwiki:`[Wiki] Evaluating AD9265, user guide <resources/eval/ad9265-fmc-125ebz>`
+
+HDL related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  :git-hdl:`AD9265-FMC HDL project source code <projects/ad9265_fmc>`
+
+.. list-table::
+   :widths: 30 35 35
+   :header-rows: 1
+
+   * - IP name
+     - Source code link
+     - Documentation link
+   * - AXI_AD9265
+     - :git-hdl:`library/axi_ad9265 <library/axi_ad9265>`
+     - :ref:`here <axi_ad9265>`
+   * - AXI_DMAC
+     - :git-hdl:`library/axi_dmac <library/axi_dmac>`
+     - :ref:`here <axi_dmac>`
+   * - AXI_CLKGEN
+     - :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
+     - :ref:`here <axi_clkgen>`
+   * - AXI_HDMI_TX
+     - :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
+     - :ref:`here <axi_hdmi_tx>`
+   * - AXI_SPDIF_TX
+     - :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
+     - ---
+   * - AXI_I2S_ADI
+     - :git-hdl:`library/axi_sysid <library/axi_i2s_adi>`
+     - ---
+   * - AXI_SYSID
+     - :git-hdl:`library/axi_sysid <library/axi_sysid>`
+     - :ref:`here <axi_sysid>`
+   * - SYSID_ROM
+     - :git-hdl:`library/sysid_rom <library/sysid_rom>`
+     - :ref:`here <axi_sysid>`
+   * - UTIL_I2C_MIXER
+     - :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
+     - :ref:`here <spi_engine offload>`
+
+Software related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- :git-linux:`Linux device tree zynq-zc706-adv7511-ad9265-fmc-125ebz.dts <arch/arm/boot/dts/zynq-zc706-adv7511-ad9265-fmc-125ebz.dts>`
+- :git-linux:`Linux driver ad9467.c <drivers/iio/adc/ad9467.c>`
+  (used for AD9265-FMC as well)
+
+.. include:: ../common/more_information.rst
+
+.. include:: ../common/support.rst

docs/projects/index.rst

@@ -33,6 +33,7 @@ Contents
    AD7616-SDZ <ad7616_sdz/index>
    AD7768-EVB <ad7768evb/index>
    AD9081/AD9082/AD9986/AD9988 <ad9081_fmca_ebz/index>
+   AD9265-FMC <ad9265_fmc/index>
    AD9434-FMC <ad9434_fmc/index>
    AD9739A-FMC <ad9739a_fmc/index>
    AD9783-EBZ <ad9783_ebz/index>

projects/ad9265_fmc/zed/Makefile

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+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad9265_fmc_zed
+
+M_DEPS += ../common/ad9265_spi.v
+M_DEPS += ../common/ad9265_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/zed/zed_system_constr.xdc
+M_DEPS += ../../common/zed/zed_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_ad9265
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_i2s_adi
+LIB_DEPS += axi_spdif_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+LIB_DEPS += util_i2c_mixer
+
+include ../../scripts/project-xilinx.mk

projects/ad9265_fmc/zed/system_bd.tcl

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+###############################################################################
+## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
+source ../common/ad9265_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file

projects/ad9265_fmc/zed/system_constr.xdc

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+###############################################################################
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# ad9265
+
+set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p]     ; ## H4   FMC_CLK0_M2C_P  IO_L12P_T1_MRCC_34
+set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n]     ; ## H5   FMC_CLK0_M2C_N  IO_L12N_T1_MRCC_34
+
+set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## D14  FMC_LA09_P      IO_L17P_T2_34
+set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## D15  FMC_LA09_N      IO_L17N_T2_34
+set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C10  FMC_LA06_P      IO_L10P_T1_34
+set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C11  FMC_LA06_N      IO_L10N_T1_34
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## H13  FMC_LA07_P      IO_L21P_T3_DQS_34
+set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## H14  FMC_LA07_N      IO_L21N_T3_DQS_34
+set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## G12  FMC_LA08_P      IO_L8P_T1_34
+set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## G13  FMC_LA08_N      IO_L8N_T1_34
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## H10  FMC_LA04_P      IO_L15P_T2_DQS_34
+set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## H11  FMC_LA04_N      IO_L15N_T2_DQS_34
+set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D11  FMC_LA05_P      IO_L7P_T1_34
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D12  FMC_LA05_N      IO_L7N_T1_34
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H7   FMC_LA02_P      IO_L20P_T3_34
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H8   FMC_LA02_N      IO_L20N_T3_34
+set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G9   FMC_LA03_P      IO_L16P_T2_34
+set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G10  FMC_LA03_N      IO_L16N_T2_34
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p]    ; ## D8   FMC_LA01_CC_P   IO_L14P_T2_SRCC_34
+set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n]    ; ## D9   FMC_LA01_CC_N   IO_L14N_T2_SRCC_34
+
+# spi
+
+set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]                    ; ## G36  FMC_LA33_P      IO_L18P_T2_AD13P_35
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]                    ; ## G37  FMC_LA33_N      IO_L18N_T2_AD13N_35
+set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_sdio]                       ; ## H37  FMC_LA32_P      IO_L15P_T2_DQS_AD12P_35
+set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk]                        ; ## H38  FMC_LA32_N      IO_L15N_T2_DQS_AD12N_35
+
+# clocks
+
+create_clock -name adc_clk      -period 8.000             [get_ports adc_clk_in_p]                  ;

projects/ad9265_fmc/zed/system_project.tcl

@@ -0,0 +1,18 @@
+###############################################################################
+## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ad9265_fmc_zed
+adi_project_files ad9265_fmc_zed [list \
+  "../common/ad9265_spi.v" \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
+
+adi_project_run ad9265_fmc_zed