lib/axi_pwm_gen: Update ext_sync-related axi_pwm_gen's logic

[alin724]

PR Description

New operation mode for the external synchronization:
External synchronization using a signal that is based on a faster clock (also compatible with slower clock than the ext_clk or axi_clk of the axi_pwm_gen module) + without using the load_config register (continuous offset-related synchronization - e.g. synchronization at 1 s by using a 1 Hz sync signal).

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[IuliaCMoldovan]

Please update the copyright year of all files to contain 2024 as well

[alin724]

V2:

• Updated the copyright year of pwm_gen lib's files to current year;

[alin724]

Update:

• can be closed for now [the implementation using 2 different cases for external sync pin of the axi_pwm_gen module [one when the ext_sync will come from a faster clock and will be used to align pwm_data to it and the second one that is from a clock that is lower and multiple of core clk] [ext_sync used with the same clock or clock lower and multiple of core_clk + using additional params [start_at_sync,ext_sync_align] from the following PR - axi_pwm_gen: New features based on parameters #1299]