Add feature for inverted LVDS data in ad_data_in and axi_ad9361

[IuliaCMoldovan]

PR Description

This started out from an EZ thread (https://ez.analog.com/fpga/f/q-a/577761/te0820-tef1002-fmcomms3-porting-fmcomms3-to-tef1002) and it seemed like a good feature to implement so it was decided to add it.

This applies only to LVDS mode!

In ad_data_in, the IBUFDS instance was replaced with an IBUFDS_DIFF_OUT such that the inverted output can be used. A parameter was added to select between inverted and normal mode.
The INV_POL parameter is interpreted as follows:

• bits 5-0 are for data lines 5-0
• bit 6 is for frame inversion
• bit 7 is for clock inversion

Changes were made in the xilinx/axi_ad9361_lvds_if.v module for having the option to invert the data and the frame for Tx, before being sent to ad_data_out.

The FMCOMMS2 base design has an INV_POL parameter added, by default set to 0.
In hardware, the FMCOMMS2/ZCU102 project was tested.

So far, we don't have a use case when we want inversion for this, in our repository.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[leetxgod]

Great work!
Please check out my comment(s).