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Add feature for inverted LVDS data in ad_data_in and axi_ad9361 #1272

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Add feature for inverted LVDS data in ad_data_in and axi_ad9361 #1272

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df64fce
ad_data_in: Add inversion parameter for data
IuliaCMoldovan Feb 7, 2024
d0101f4
axi_ad9361: Add support for inversion of data
IuliaCMoldovan Feb 8, 2024
ce155a4
fmcomms2_bd.tcl: Add INV_POL parameter
IuliaCMoldovan Feb 8, 2024
365b3a3
add option to invert clock polarity
IuliaCMoldovan Feb 13, 2024
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14 changes: 9 additions & 5 deletions library/axi_ad9361/axi_ad9361.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -37,8 +37,6 @@

module axi_ad9361 #(

// parameters

parameter ID = 0,
parameter MODE_1R1T = 0,
parameter FPGA_TECHNOLOGY = 0,
Expand Down Expand Up @@ -70,7 +68,12 @@ module axi_ad9361 #(
parameter MIMO_ENABLE = 0,
parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter RX_NODPA = 0
parameter RX_NODPA = 0,
// for lvds mode only -- polarity inversion for each line and for frame
// bits 5:0 - per line inversion of data in ad_data_in, lines 5-0
// bit 6 - frame inversion
// i.e.: 64 means inversion on all 5 lines and frame as well
parameter INV_POL = 0
) (

// physical interface (receive-lvds)
Expand Down Expand Up @@ -408,7 +411,8 @@ module axi_ad9361 #(
.CLK_DESKEW (MIMO_ENABLE),
.USE_SSI_CLK (USE_SSI_CLK),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.RX_NODPA (RX_NODPA)
.RX_NODPA (RX_NODPA),
.INV_POL (INV_POL)
) i_dev_if (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
Expand Down
54 changes: 37 additions & 17 deletions library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -44,7 +44,12 @@ module axi_ad9361_lvds_if #(
parameter CLK_DESKEW = 0,
parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter RX_NODPA = 0
parameter RX_NODPA = 0,
// for lvds mode only -- polarity inversion for each line and for frame
// bits 5:0 - per line inversion of data in ad_data_in, lines 5-0
// bit 6 - frame inversion
// i.e.: 64 means inversion on all 5 lines and frame as well
parameter INV_POL = 0
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) (

// physical interface (receive)
Expand Down Expand Up @@ -146,9 +151,9 @@ module axi_ad9361_lvds_if #(
reg [ 5:0] tx_data_0_p = 'd0;
reg [ 5:0] tx_data_1_p = 'd0;
reg [ 1:0] tx_clk = 'd0;
reg tx_frame = 'd0;
reg [ 5:0] tx_data_0 = 'd0;
reg [ 5:0] tx_data_1 = 'd0;
reg tx_frame_r = 'd0;
reg [ 5:0] tx_data_0_r = 'd0;
reg [ 5:0] tx_data_1_r = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
Expand All @@ -166,6 +171,13 @@ module axi_ad9361_lvds_if #(
wire [ 5:0] rx_data_0_s;
wire [ 1:0] rx_frame_s;
wire locked_s;
wire tx_frame_s;
wire [ 5:0] tx_data_0_s;
wire [ 5:0] tx_data_1_s;

// local parameters

localparam [6:0] INV_POL_PER_LINE = INV_POL;

// drp interface signals

Expand Down Expand Up @@ -373,18 +385,18 @@ module axi_ad9361_lvds_if #(

always @(posedge l_clk) begin
tx_clk <= tx_clk_n;
tx_frame <= tx_frame_n;
tx_data_0 <= tx_data_0_n;
tx_data_1 <= tx_data_1_n;
tx_frame_r <= tx_frame_n;
tx_data_0_r <= tx_data_0_n;
tx_data_1_r <= tx_data_1_n;
end

end else begin /* CLK_DESKEW == 0 */

always @(posedge l_clk) begin
tx_clk <= tx_clk_p;
tx_frame <= tx_frame_p;
tx_data_0 <= tx_data_0_p;
tx_data_1 <= tx_data_1_p;
tx_frame_r <= tx_frame_p;
tx_data_0_r <= tx_data_0_p;
tx_data_1_r <= tx_data_1_p;
end

end
Expand Down Expand Up @@ -455,7 +467,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.INV_POL (INV_POL_PER_LINE[i])
) i_rx_data (
.rx_clk (l_clk),
.rx_data_in_p (rx_data_in_p[i]),
Expand All @@ -478,7 +491,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (IODELAY_CTRL),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.INV_POL (INV_POL_PER_LINE[6])
) i_rx_frame (
.rx_clk (l_clk),
.rx_data_in_p (rx_frame_in_p),
Expand All @@ -497,6 +511,10 @@ module axi_ad9361_lvds_if #(

generate
for (i = 0; i < 6; i = i + 1) begin: g_tx_data

assign tx_data_1_s[i] = (INV_POL_PER_LINE[i] == 1) ? ~tx_data_1_r[i] : tx_data_1_r[i];
assign tx_data_0_s[i] = (INV_POL_PER_LINE[i] == 1) ? ~tx_data_0_r[i] : tx_data_0_r[i];

ad_data_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
Expand All @@ -505,8 +523,8 @@ module axi_ad9361_lvds_if #(
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_data_1[i]),
.tx_data_n (tx_data_0[i]),
.tx_data_p (tx_data_1_s[i]),
.tx_data_n (tx_data_0_s[i]),
.tx_data_out_p (tx_data_out_p[i]),
.tx_data_out_n (tx_data_out_n[i]),
.up_clk (up_clk),
Expand All @@ -521,6 +539,8 @@ module axi_ad9361_lvds_if #(

// transmit frame interface, oddr -> obuf

assign tx_frame_s = (INV_POL_PER_LINE[6] == 1) ? ~tx_frame_r : tx_frame_r;

ad_data_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
Expand All @@ -529,8 +549,8 @@ module axi_ad9361_lvds_if #(
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_frame),
.tx_data_n (tx_frame),
.tx_data_p (tx_frame_s),
.tx_data_n (tx_frame_s),
.tx_data_out_p (tx_frame_out_p),
.tx_data_out_n (tx_frame_out_n),
.up_clk (up_clk),
Expand Down
18 changes: 14 additions & 4 deletions library/xilinx/common/ad_data_in.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -49,7 +49,9 @@ module ad_data_in #(
parameter IODELAY_ENABLE = 1,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group",
parameter REFCLK_FREQUENCY = 200
parameter REFCLK_FREQUENCY = 200,
// for lvds mode only
parameter INV_POL = 0
) (

// data interface
Expand Down Expand Up @@ -122,6 +124,11 @@ module ad_data_in #(
// internal signals

wire rx_data_ibuf_s;
// rx_data_ibuf_s inverted, taken from OB port of IBUFDS_DIFF_OUT
// check-out the doc here: https://docs.xilinx.com/r/2023.1-English/ug974-vivado-ultrascale-libraries/IBUFDS_DIFF_OUT
wire rx_data_ibuf_inv_s;
// the not inverted version
wire rx_data_ibuf_not_inv_s;
wire rx_data_idelay_s;
wire [ 8:0] up_drdata_s;

Expand Down Expand Up @@ -169,10 +176,13 @@ module ad_data_in #(
.I (rx_data_in_p),
.O (rx_data_ibuf_s));
end else begin
IBUFDS i_rx_data_ibuf (
IBUFDS_DIFF_OUT i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
.O (rx_data_ibuf_not_inv_s),
.OB (rx_data_ibuf_inv_s));

assign rx_data_ibuf_s = (INV_POL == 1) ? rx_data_ibuf_inv_s : rx_data_ibuf_not_inv_s;
end
endgenerate

Expand Down
3 changes: 2 additions & 1 deletion projects/fmcomms2/common/fmcomms2_bd.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -32,6 +32,7 @@ create_bd_port -dir O tdd_sync_t

ad_ip_instance axi_ad9361 axi_ad9361
ad_ip_parameter axi_ad9361 CONFIG.ID 0
ad_ip_parameter axi_ad9361 CONFIG.INV_POL 0

# set to 1 for CORDIC or 2 for POLYNOMIAL
ad_ip_parameter axi_ad9361 CONFIG.DAC_DDS_TYPE 1
Expand Down
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