Create interconnect test based on example SoC in soc generator

Internal-tag: [#49811]
Signed-off-by: Krzysztof Obłonczek <koblonczek@internships.antmicro.com>

.ci.yml

@@ -3,13 +3,15 @@ stages:
   - build
   - deploy
 
-image: debian:bullseye
+image: debian:bookworm
 
 lint:
   stage: test
   before_script: &BeforeScript
     - apt-get update -qq
-    - apt-get install -y --no-install-recommends python3-pip
+    - apt-get install -y --no-install-recommends python3-pip python3-venv
+    - python3 -m venv venv
+    - source venv/bin/activate
     - python3 -m pip install -U pip wheel setuptools
   script:
     - python3 -m pip install -r requirements.dev.txt
@@ -19,9 +21,18 @@ pytest:
   stage: test
   variables:
     GIT_SUBMODULE_STRATEGY: normal
-  before_script: *BeforeScript
+  before_script:
+    - apt-get update -qq
+    - apt-get install -y --no-install-recommends wget git python3-dev python3-venv make ninja-build gcc-riscv64-unknown-elf bsdextrautils verilator
+    - mkdir -p miniconda3
+    - wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda3/miniconda.sh
+    - bash miniconda3/miniconda.sh -b -u -p miniconda3
+    - rm -rf miniconda3/miniconda.sh
+    - source miniconda3/bin/activate
+    - conda create -n venv python=3.9
+    - conda activate venv
+    - conda install -c conda-forge gcc=12.1.0
   script:
-    - apt-get install -y --no-install-recommends git python3-dev
     - python3 -m pip install -r requirements.dev.txt
     - python3 -m pip install git+https://github.com/antmicro/tuttest
     - tuttest README.md | bash -

tests/data/data_build/interconnect/ipcores/VexRiscv.yaml

@@ -0,0 +1,42 @@
+signals:
+  in:
+    - [externalResetVector, 31, 0]
+    - timerInterrupt
+    - softwareInterrupt
+    - [externalInterruptArray, 31, 0]
+    - clk
+    - reset
+m_dbus_wishbone:
+  interface: wishbone
+  mode: master
+  signals:
+    in:
+      ack: dBusWishbone_ACK
+      dat_r: [dBusWishbone_DAT_MISO, 31, 0]
+      err: dBusWishbone_ERR
+    out:
+      cyc: dBusWishbone_CYC
+      stb: dBusWishbone_STB
+      we: dBusWishbone_WE
+      adr: [dBusWishbone_ADR, 29, 0]
+      dat_w: [dBusWishbone_DAT_MOSI, 31, 0]
+      sel: [dBusWishbone_SEL, 3, 0]
+      cti: [dBusWishbone_CTI, 2, 0]
+      bte: [dBusWishbone_BTE, 1, 0]
+m_ibus_wishbone:
+  interface: wishbone
+  mode: master
+  signals:
+    in:
+      ack: iBusWishbone_ACK
+      dat_r: [iBusWishbone_DAT_MISO, 31, 0]
+      err: iBusWishbone_ERR
+    out:
+      cyc: iBusWishbone_CYC
+      stb: iBusWishbone_STB
+      we: iBusWishbone_WE
+      adr: [iBusWishbone_ADR, 29, 0]
+      dat_w: [iBusWishbone_DAT_MOSI, 31, 0]
+      sel: [iBusWishbone_SEL, 3, 0]
+      cti: [iBusWishbone_CTI, 2, 0]
+      bte: [iBusWishbone_BTE, 1, 0]

tests/data/data_build/interconnect/ipcores/crg.yaml

@@ -0,0 +1,6 @@
+signals:
+  in:
+    - clk100
+  out:
+    - sys_clk
+    - sys_rst

tests/data/data_build/interconnect/ipcores/litex_mem.yaml

@@ -0,0 +1,22 @@
+signals:
+  in:
+    - sys_clk
+    - sys_rst
+  out: []
+s_wishbone:
+  interface: wishbone
+  mode: slave
+  signals:
+    in:
+      adr: [mem_bus_adr, 29, 0]
+      dat_w: [mem_bus_dat_w, 31, 0]
+      sel: [mem_bus_sel, 3, 0]
+      we: mem_bus_we
+      bte: [mem_bus_bte, 1, 0]
+      cti: [mem_bus_cti, 2, 0]
+      cyc: mem_bus_cyc
+      stb: mem_bus_stb
+    out:
+      ack: mem_bus_ack
+      err: mem_bus_err
+      dat_r: [mem_bus_dat_r, 31, 0]

tests/data/data_build/interconnect/ipcores/soc.yaml

@@ -0,0 +1,62 @@
+signals:
+  in:
+    - sys_clk
+    - sys_rst
+    - sim_serial_source_ready
+    - sim_serial_sink_valid
+    - [sim_serial_sink_data, 7, 0]
+  out:
+    - sim_serial_sink_ready
+    - sim_serial_source_valid
+    - [sim_serial_source_data, 7, 0]
+m_dbus_wishbone:
+  interface: wishbone
+  mode: master
+  signals:
+    in:
+      ack: dbus_ack
+      dat_r: [dbus_dat_r, 31, 0]
+      err: dbus_err
+    out:
+      cyc: dbus_cyc
+      stb: dbus_stb
+      we: dbus_we
+      adr: [dbus_adr, 29, 0]
+      dat_w: [dbus_dat_w, 31, 0]
+      sel: [dbus_sel, 3, 0]
+      cti: [dbus_cti, 2, 0]
+      bte: [dbus_bte, 1, 0]
+m_ibus_wishbone:
+  interface: wishbone
+  mode: master
+  signals:
+    in:
+      ack: ibus_ack
+      dat_r: [ibus_dat_r, 31, 0]
+      err: ibus_err
+    out:
+      cyc: ibus_cyc
+      stb: ibus_stb
+      we: ibus_we
+      adr: [ibus_adr, 29, 0]
+      dat_w: [ibus_dat_w, 31, 0]
+      sel: [ibus_sel, 3, 0]
+      cti: [ibus_cti, 2, 0]
+      bte: [ibus_bte, 1, 0]
+s_csr_wishbone:
+  interface: wishbone
+  mode: slave
+  signals:
+    in:
+      cyc: csr_wishbone_cyc
+      stb: csr_wishbone_stb
+      we: csr_wishbone_we
+      adr: [csr_wishbone_adr, 29, 0]
+      dat_w: [csr_wishbone_dat_w, 31, 0]
+      sel: [csr_wishbone_sel, 3, 0]
+      cti: [csr_wishbone_cti, 2, 0]
+      bte: [csr_wishbone_bte, 1, 0]
+    out:
+      ack: csr_wishbone_ack
+      dat_r: [csr_wishbone_dat_r, 31, 0]
+      err: csr_wishbone_err

tests/data/data_build/interconnect/project.yml

@@ -0,0 +1,89 @@
+ips:
+  soc:
+    file: ipcores/soc.yaml
+    module: soc
+  wb_ram_data:
+    file: ipcores/litex_mem.yaml
+    module: mem
+  wb_ram_instr:
+    file: ipcores/litex_mem.yaml
+    module: mem
+  crg:
+    file: ipcores/crg.yaml
+    module: crg
+
+design:
+  name: top
+  parameters:
+    soc: {}
+    crg: {}
+    wb_ram_data:
+      depth: 0x1000
+      memfile: "top_sram.init"
+    wb_ram_instr:
+      depth: 0xA000
+      memfile: "top_rom.init"
+  ports:
+    wb_ram_data:
+      sys_clk: clk100
+      sys_rst: [crg, sys_rst]
+    wb_ram_instr:
+      sys_clk: clk100
+      sys_rst: [crg, sys_rst]
+    crg:
+      clk100: clk100
+    soc:
+      sys_clk: clk100
+      sys_rst: [crg, sys_rst]
+      sim_serial_source_ready: sim_serial_source_ready
+      sim_serial_sink_valid: sim_serial_sink_valid
+      sim_serial_sink_data: sim_serial_sink_data
+      sim_serial_sink_ready: sim_serial_sink_ready
+      sim_serial_source_valid: sim_serial_source_valid
+      sim_serial_source_data: sim_serial_source_data
+  interfaces: {}
+  interconnects:
+    interconnect0:
+      clock: clk100
+      reset: [crg, sys_rst]
+      type: wishbone_roundrobin
+      params:
+        addr_width: 30
+        data_width: 32
+        granularity: 8
+        features: ["bte", "cti", "err"]
+      slaves:
+        wb_ram_instr:
+          s_wishbone:
+            address: 0x00000000
+            size: 0xA000
+        wb_ram_data:
+          s_wishbone:
+            address: 0x10000000
+            size: 0x1000
+        soc:
+          s_csr_wishbone:
+            address: 0xF0000000
+            size: 0x1000
+      masters:
+        soc:
+          - m_dbus_wishbone
+          - m_ibus_wishbone
+
+external:
+  ports:
+    in:
+      - clk100
+      - sim_serial_source_ready
+      - sim_serial_sink_valid
+      - sim_serial_sink_data
+    out:
+      - sim_serial_sink_ready
+      - sim_serial_source_valid
+      - sim_serial_source_data
+    inout: []
+  interfaces:
+    in: []
+    out: []
+    inout: []
+

tests/data/data_build/interconnect/sources/crg.v

@@ -0,0 +1,24 @@
+/* Machine-generated using Migen */
+module crg(
+	input clk100,
+	output sys_clk,
+	output sys_rst
+);
+
+wire por_clk;
+reg int_rst = 1'd1;
+
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+
+assign sys_clk = clk100;
+assign por_clk = clk100;
+assign sys_rst = int_rst;
+
+always @(posedge por_clk) begin
+	int_rst <= 1'd0;
+end
+
+endmodule

tests/data/data_build/interconnect/sources/mem.v

@@ -0,0 +1,70 @@
+module mem #(
+	parameter depth = 256,
+	parameter memfile = ""
+)(
+	input [29:0] mem_bus_adr,
+	input [31:0] mem_bus_dat_w,
+	output [31:0] mem_bus_dat_r,
+	input [3:0] mem_bus_sel,
+	input mem_bus_cyc,
+	input mem_bus_stb,
+	output reg mem_bus_ack,
+	input mem_bus_we,
+	input [2:0] mem_bus_cti,
+	input [1:0] mem_bus_bte,
+	input mem_bus_err,
+	input sys_clk,
+	input sys_rst
+);
+
+localparam aw = $clog2(depth);
+
+reg adr_burst = 1'd0;
+wire [aw-1:0] adr;
+wire [31:0] dat_r;
+reg [3:0] we;
+wire [31:0] dat_w;
+
+
+always @(*) begin
+	we <= 4'd0;
+	we[0] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[0]);
+	we[1] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[1]);
+	we[2] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[2]);
+	we[3] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[3]);
+end
+assign adr = mem_bus_adr[aw-1:0];
+assign mem_bus_dat_r = dat_r;
+assign dat_w = mem_bus_dat_w;
+
+always @(posedge sys_clk) begin
+	mem_bus_ack <= 1'd0;
+	if (((mem_bus_cyc & mem_bus_stb) & ((~mem_bus_ack) | adr_burst))) begin
+		mem_bus_ack <= 1'd1;
+	end
+	if (sys_rst) begin
+		mem_bus_ack <= 1'd0;
+	end
+end
+
+reg [31:0] mem[0:depth-1];
+reg [aw-1:0] memadr;
+always @(posedge sys_clk) begin
+	if (we[0])
+		mem[adr][7:0] <= dat_w[7:0];
+	if (we[1])
+		mem[adr][15:8] <= dat_w[15:8];
+	if (we[2])
+		mem[adr][23:16] <= dat_w[23:16];
+	if (we[3])
+		mem[adr][31:24] <= dat_w[31:24];
+	memadr <= adr;
+end
+
+assign dat_r = mem[memadr];
+
+initial begin
+	$readmemh(memfile, mem);
+end
+
+endmodule