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Feature: Initial RISC-V debug support (v0.13 spec) #1380
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…nd what kinds of triggers they each support
…h and breakpoints
…operation on rv64
…ledgement of the reset
…ng unsuitable trigger slots
…rmat and store it as a DMI designer code
…djust for BMD's representation of JEP-106 codes
…ose some CSRs register in the xml description
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esden
approved these changes
Oct 31, 2023
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Fantastic! Finally! Thank you!
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Detailed description
In this PR we implement support for debugging RISC-V targets complying with v0.13.2 of the RISC-V debug specification. This includes support for both rv32 and rv64 targets and intentionally fails to work with rv128 targets (though we still must detect those).
This PR also introduces support for the GD32VF1 series through minimal changes to stm32f1.c, providing a test target to play with.
Known limitations include:
This PR replaces #924.
Your checklist for this pull request
make PROBE_HOST=native
)make PROBE_HOST=hosted
)Closing issues
Fixes #794