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Feature: Initial RISC-V debug support (v0.13 spec) #1380

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merged 62 commits into from
Oct 31, 2023
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13684c6
riscv_debug: Begun building a scan handler for RISC-V debug v0.13 dev…
dragonmux Feb 8, 2023
d955617
riscv_debug: Created a stub for initialising a DMI
dragonmux Feb 8, 2023
f827d4b
riscv_debug: Implemented a way to read/write the DTM control/status r…
dragonmux Feb 8, 2023
637f5f9
riscv_debug: Moved the JTAG-specific DTM handler into the JTAG DTM im…
dragonmux Mar 21, 2023
be66247
riscv_debug: Implemented support for reading and dispatching the DTM …
dragonmux Feb 8, 2023
55e8550
riscv_debug: Implemented reference counting and stub structures for t…
dragonmux Feb 8, 2023
0f3ce8d
riscv_debug: Restructed riscv_dmi_init() and riscv_jtag_dtm_init() to…
dragonmux Feb 8, 2023
1aefd61
riscv_debug: Handle the idle cycles component of the DTMCS register
dragonmux Feb 8, 2023
95a5d4d
riscv_debug: Implemented a way to read the DMI address space
dragonmux Feb 8, 2023
9ab2ad6
riscv_debug: Implemented logic for iterating and discovering DMs
dragonmux Feb 8, 2023
1a33d28
riscv_debug: Begun implementing the hart enumeration process
dragonmux Feb 8, 2023
104cfb3
riscv_debug: Implemented enumeration of the harts associated with a DM
dragonmux Feb 8, 2023
9494851
riscv_debug: Implemented support for grabbing the hart's address bus …
dragonmux Feb 8, 2023
f021934
riscv_debug: Implemented halt and resume support in preparation for r…
dragonmux Feb 8, 2023
582fefb
riscv_debug: Implemented readout of CSRs and reading the 4 hart ident…
dragonmux Feb 8, 2023
c9387aa
riscv_debug: Implemented readout of the ISA register to determine add…
dragonmux Feb 8, 2023
00752f7
riscv_debug: Implemented the ability for riscv_reg_read() to do 128-,…
dragonmux Feb 9, 2023
b59b369
riscv_debug: Implemented support for discovering the target Hart's IS…
dragonmux Feb 9, 2023
dafc14d
riscv_debug: Implemented writing to CSRs
dragonmux Feb 9, 2023
aa4f8b6
riscv_debug: Created probe stubs for probing RISC-V 32- and 64-bit ta…
dragonmux Feb 9, 2023
d8d70a2
riscv_debug: Set up the target designer code field
dragonmux Feb 9, 2023
825f622
riscv_debug: Documented the used CSR addresses
dragonmux Feb 9, 2023
4297679
riscv_debug: Implemented the ability to force a CSR access to a speci…
dragonmux Feb 9, 2023
9935f0a
riscv_debug: Implemented single-stepping support in riscv_halt_resume()
dragonmux Feb 9, 2023
d199ea4
riscv_debug: Added definitions for the abstract memory access command
dragonmux Feb 9, 2023
ba89798
riscv_debug: Implemented arbitrary memory read
dragonmux Feb 9, 2023
33ef9b5
riscv_debug: Fixed the target hart not being halted during probing
dragonmux Feb 9, 2023
d567386
riscv_debug: Added some DEBUG_TARGET information to the CSR functions…
dragonmux Feb 9, 2023
ab75c95
riscv_debug: Implemented the target check_error hook
dragonmux Feb 9, 2023
b018366
riscv_debug: Made more of the DM and hart machinary available in the …
dragonmux Feb 9, 2023
65a1d8e
riscv_debug: Moved the mem_read implementation into the bitness-speci…
dragonmux Feb 9, 2023
790a3fc
riscv_debug: Forced the vendor ID to be read 32-bit per the privilege…
dragonmux Feb 9, 2023
1bb0332
riscv_debug: Handle the rv128 case by complaining to the user we don'…
dragonmux Feb 9, 2023
9a91735
riscv_debug: Begun implementing attach/detach
dragonmux Feb 9, 2023
f84c117
riscv_debug: Implemented building the target description XML
dragonmux Feb 10, 2023
c9ea2aa
riscv_debug: Implemented regs_read for both rv32 and rv64
dragonmux Feb 10, 2023
3d024a2
riscv_debug: Halt the hart we're looking at to on attach, and resume …
dragonmux Feb 10, 2023
7727bd1
riscv32: Added some better documentation for what various things do
dragonmux Feb 10, 2023
07f80cc
riscv64: Added some better documentation for what various things do
dragonmux Feb 10, 2023
ce008df
riscv_debug: Fixed a couple of mistakes in the comments for riscv_dmi…
dragonmux Feb 10, 2023
7f892b7
riscv_debug: Implemented the target halt_poll hook
dragonmux Feb 10, 2023
ffbef8d
riscv_debug: Implemented discovery of the available "trigger" slots a…
dragonmux Feb 10, 2023
bbec2b1
riscv_debug: Implemented support machinary for being able to set watc…
dragonmux Feb 10, 2023
0cceab3
riscv_debug: Added documentation on where to find the debug specs used
dragonmux Feb 10, 2023
6e58808
riscv_debug: Implemented a translator for a breakwatch size to match …
dragonmux Feb 10, 2023
8fb27fd
riscv32: Implemented the target breakwatch_set hook
dragonmux Feb 10, 2023
f8e3c0c
riscv32: Implemented the target breakwatch_clear hook
dragonmux Feb 10, 2023
8c7059f
gdb_main: Added some comments to aid with understanding handle_z_pack…
dragonmux Feb 10, 2023
da2f94a
riscv_debug: Moved the part ID readout into its own function, fixing …
dragonmux Feb 11, 2023
0f392b3
riscv_debug: Implemented target reset
dragonmux Feb 11, 2023
c9ed334
riscv_debug: Refactored out the DM state polling code into a new func…
dragonmux Feb 11, 2023
c485fd6
riscv_debug: Implemented polling for reset succeeding and then acknow…
dragonmux Feb 11, 2023
8dad8bb
riscv32: Improved the checks in riscv32_breakwatch_set() to avoid usi…
dragonmux Feb 11, 2023
89846d3
riscv_debug: Cleaned up the nomenclature of riscv_halt_poll()'s halt …
dragonmux Feb 11, 2023
330beee
riscv_debug: Implemented regs_write for both rv32 and rv64
dragonmux Feb 11, 2023
fd6bf73
riscv32: Implemented mem_write and a data packing helper
dragonmux Feb 11, 2023
b7c38b5
riscv_debug: Transform JTAG ID Code designer into JEP-106 internal fo…
perigoso Feb 19, 2023
690cbd2
riscv_debug: Fixed the vendor ID decode in riscv_hart_read_ids() to a…
dragonmux Mar 28, 2023
037a35f
riscv_debug: Implemented poll timeouts for halt/resume
dragonmux Apr 1, 2023
7d936f9
riscv: check if hw reset worked, if not do a DM reset
Aug 13, 2023
a032220
riscv: make sure the hart is stopped when exiting reset
Aug 15, 2023
11ec1f1
riscv: add single register access, add csr access with an offset, exp…
Aug 15, 2023
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10 changes: 10 additions & 0 deletions src/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ PLATFORM_DIR = platforms/$(PROBE_HOST)
VPATH += $(PLATFORM_DIR) target
ENABLE_DEBUG ?= 0
ENABLE_CORTEXAR ?= 0
ENABLE_RISCV ?= 0

SYS = $(shell $(CC) -dumpmachine)

Expand Down Expand Up @@ -94,6 +95,15 @@ CFLAGS += -DENABLE_CORTEXAR
SRC += cortexar.c
endif

ifeq ($(ENABLE_RISCV), 1)
CFLAGS += -DENABLE_RISCV
SRC += \
riscv32.c \
riscv64.c \
riscv_debug.c \
riscv_jtag_dtm.c
endif

ifneq ($(PC_HOSTED),1)
# Output memory usage information
LDFLAGS += -Wl,--print-memory-usage
Expand Down
3 changes: 3 additions & 0 deletions src/gdb_main.c
Original file line number Diff line number Diff line change
Expand Up @@ -721,10 +721,13 @@ static void handle_z_packet(char *packet, const size_t plen)
else
ret = target_breakwatch_clear(cur_target, type, addr, len);

/* If the target handler was unable to set/clear the break/watch-point, return an error */
if (ret < 0)
gdb_putpacketz("E01");
/* If the handler does not support the kind requested, return empty string */
else if (ret > 0)
gdb_putpacketz("");
/* Otherwise let GDB know that everything went well */
else
gdb_putpacketz("OK");
}
Expand Down
1 change: 1 addition & 0 deletions src/platforms/hosted/Makefile.inc
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ CFLAGS += -DENABLE_DEBUG -DPLATFORM_HAS_DEBUG
CFLAGS +=-I ./target

ENABLE_CORTEXAR := 1
ENABLE_RISCV := 1

# Clang requires some special handling here: -gnu means MinGW
# while -msvc means Clang/CL. We don't currently support the latter
Expand Down
5 changes: 5 additions & 0 deletions src/target/adiv5.h
Original file line number Diff line number Diff line change
Expand Up @@ -207,6 +207,11 @@
#define JTAG_IDCODE_PARTNO_MASK (0xffffU << JTAG_IDCODE_PARTNO_OFFSET)
#define JTAG_IDCODE_DESIGNER_OFFSET 1U
#define JTAG_IDCODE_DESIGNER_MASK (0x7ffU << JTAG_IDCODE_DESIGNER_OFFSET)
/* Bits 10:7 - JEP-106 Continuation code */
/* Bits 6:0 - JEP-106 Identity code */
#define JTAG_IDCODE_DESIGNER_JEP106_CONT_OFFSET 7U
#define JTAG_IDCODE_DESIGNER_JEP106_CONT_MASK (0xfU << ADIV5_DP_DESIGNER_JEP106_CONT_OFFSET)
#define JTAG_IDCODE_DESIGNER_JEP106_CODE_MASK (0x7fU)

#define JTAG_IDCODE_PARTNO_DPv0 0xba00U

Expand Down
8 changes: 5 additions & 3 deletions src/target/jtag_devs.c
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@
#include "general.h"
#include "jtag_scan.h"
#include "adiv5.h"
#include "riscv_debug.h"
#include "jtag_devs.h"

const jtag_dev_descr_s dev_descr[] = {
Expand Down Expand Up @@ -349,9 +350,10 @@ const jtag_dev_descr_s dev_descr[] = {
},
#ifdef ENABLE_DEBUG
{
.idcode = 0x0000063dU,
.idmask = 0x00000fffU,
.descr = "Xambala: RVDBG013.",
.idcode = 0x0000563dU,
.idmask = 0x0fffffffU,
.descr = "RISC-V debug v0.13.",
.handler = riscv_jtag_dtm_handler,
},
{
.idcode = 0x000007a3U,
Expand Down
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