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SymbolTable: Gracefully handle current CHECK-fail #2029

Merged
merged 1 commit into from
Oct 21, 2023
Merged

SymbolTable: Gracefully handle current CHECK-fail #2029

merged 1 commit into from
Oct 21, 2023

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hzeller
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@hzeller hzeller commented Oct 19, 2023

This situation seems to arise if we have possibly multiple parent references when fed a bunch of possibly unrelated files with naming overlap. Don't crash in this case.

This situation seems to arise if we have possibly multiple parent references
when fed a bunch of possibly unrelated files with naming overlap. Don't
crash in this case.
@hzeller hzeller requested a review from fangism October 19, 2023 23:58
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Codecov Report

Attention: 7 lines in your changes are missing coverage. Please review.

Comparison is base (470e0b9) 92.85% compared to head (3681b01) 92.84%.
Report is 6 commits behind head on master.

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Additional details and impacted files
@@            Coverage Diff             @@
##           master    #2029      +/-   ##
==========================================
- Coverage   92.85%   92.84%   -0.01%     
==========================================
  Files         357      357              
  Lines       26399    26396       -3     
==========================================
- Hits        24512    24507       -5     
- Misses       1887     1889       +2     
Files Coverage Δ
common/text/concrete_syntax_tree.cc 100.00% <100.00%> (ø)
common/text/concrete_syntax_tree.h 96.82% <100.00%> (+0.46%) ⬆️
common/text/tree_builder_test_util.cc 100.00% <100.00%> (ø)
common/text/tree_utils.cc 97.27% <100.00%> (-0.02%) ⬇️
common/text/tree_utils.h 100.00% <100.00%> (ø)
verilog/CST/expression.cc 96.10% <100.00%> (-0.10%) ⬇️
verilog/CST/macro.cc 100.00% <100.00%> (ø)
verilog/CST/module.cc 100.00% <100.00%> (ø)
verilog/CST/port.cc 94.36% <100.00%> (ø)
verilog/CST/seq_block.cc 100.00% <100.00%> (ø)
... and 15 more

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@hzeller hzeller merged commit 66c8c26 into chipsalliance:master Oct 21, 2023
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3 participants