build(deps): bump third_party/litex from 95b310e
to 1ab8563
#3468
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Bumps third_party/litex from
95b310e
to1ab8563
.Commits
1ab8563
tools/litex_server, tools/remote/comm_udp: fix Etherbonexx constructors by pa...4610713
gen/fhdl/verilog: Ensure top is not None to build hierarchy.862a0db
Merge pull request #1829 from enjoy-digital/kianv6598fe9
cores/cpu: Add KianV CPU (RV32IMA) initial support.c1e4b3a
xilinx/clock: Add reset_buf parameter to allow using a buffer to route reset ...d0bb837
Merge pull request #1828 from enjoy-digital/verilog_improvements_2657252c
gen/fhdl/namer: Update copyrights.5b989bc
gen/fhdl/verilog: Switch Assign/Operator types to IntEnum.33fd774
interconnect/stream/ClockDomainCrossing: Use DUID for clock_domain id to allo...ef4235a
gen/fhdl/namer: Use _ for private functions and remove build_namespace.Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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