Reimagining CPU Architecture from the Outside: Pursuing the 5M-strat through unconventional logic design.
ποΈ My 5 Core Philosophy: 5M-strat All architectural designs in this repository are optimized based on the "5M-strat" to achieve the perfect balance between engineering efficiency and user experience.
π Minimum (For efficiency)
- Minimum Clock: Prioritizing logic optimization over high clock speeds to ensure stability, compensated by high IPC and optimizations.
- Minimum Power: Drastically reducing power consumption for sustainable mobile environments.
- Minimum Area: Optimizing die size to improve production costs, leakage current and yield rates.
π Maximum (For value) 4. Maximum Performance: Delivering peak computational power relative to area and power constraints. 5. Maximum UX: Focusing on real-world responsiveness and smoothness that users actually feel.
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π μ΅μν (ν¨μ¨μ μν μ΅μν)
- μ΅μν΄λ: λΆνμν κ³ ν΄λμ μ§μνκ³ κ³ IPC/μ΅μ νλ‘ λ체
- μ΅μμ λ ₯: μ λ ₯ ν¨μ¨μ κ·Ήλννμ¬ λͺ¨λ°μΌ νκ²½μ μ΅μ ν
- μ΅μλ©΄μ : μΉ© λ©΄μ μ μ΅μννμ¬ μμ° λ¨κ°, λμ€ μ λ₯ λ° μμ¨ κ°μ
π μ΅λν (μ±λ₯μ μν μ΅λν)
4. μ΅λμ±λ₯: λμΌ λ©΄μ /μ λ ₯ λλΉ μ΅μμ μ°μ° μ±λ₯ λμΆ
5. μ΅λUX: μ€μ μ¬μ©μκ° μ²΄κ°νλ λ°μ μλμ λΆλλ¬μ μ΅μ°μ