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Architecture

Reimagining CPU Architecture from the Outside: Pursuing the 5M-strat through unconventional logic design.

πŸ›οΈ My 5 Core Philosophy: 5M-strat All architectural designs in this repository are optimized based on the "5M-strat" to achieve the perfect balance between engineering efficiency and user experience.

πŸ“‰ Minimum (For efficiency)

  1. Minimum Clock: Prioritizing logic optimization over high clock speeds to ensure stability, compensated by high IPC and optimizations.
  2. Minimum Power: Drastically reducing power consumption for sustainable mobile environments.
  3. Minimum Area: Optimizing die size to improve production costs, leakage current and yield rates.

πŸ“ˆ Maximum (For value) 4. Maximum Performance: Delivering peak computational power relative to area and power constraints. 5. Maximum UX: Focusing on real-world responsiveness and smoothness that users actually feel.

πŸ›οΈ 핡심 μ² ν•™ 5κ°€μ§€: 5졜 μ² ν•™ λͺ¨λ“  제 μ•„ν‚€ν…μ²˜ μ„€κ³„λŠ” '5졜 μ² ν•™'을 κΈ°μ€€μœΌλ‘œ μ„€κ³„λ˜κ³  μ΅œμ ν™”λ©λ‹ˆλ‹€.

πŸ“‰ μ΅œμ†Œν™” (νš¨μœ¨μ„ μœ„ν•œ μ΅œμ†Œν™”)

  1. μ΅œμ†Œν΄λŸ­: λΆˆν•„μš”ν•œ κ³ ν΄λŸ­μ„ μ§€μ–‘ν•˜κ³  κ³  IPC/μ΅œμ ν™”λ‘œ λŒ€μ²΄
  2. μ΅œμ†Œμ „λ ₯: μ „λ ₯ νš¨μœ¨μ„ κ·ΉλŒ€ν™”ν•˜μ—¬ λͺ¨λ°”일 ν™˜κ²½μ— μ΅œμ ν™”
  3. μ΅œμ†Œλ©΄μ : μΉ© 면적을 μ΅œμ†Œν™”ν•˜μ—¬ 생산 단가, λˆ„μ„€ μ „λ₯˜ 및 수율 κ°œμ„ 

πŸ“ˆ μ΅œλŒ€ν™” (μ„±λŠ₯을 μœ„ν•œ μ΅œλŒ€ν™”)
4. μ΅œλŒ€μ„±λŠ₯: 동일 면적/μ „λ ₯ λŒ€λΉ„ μ΅œμƒμ˜ μ—°μ‚° μ„±λŠ₯ λ„μΆœ
5. μ΅œλŒ€UX: μ‹€μ œ μ‚¬μš©μžκ°€ μ²΄κ°ν•˜λŠ” λ°˜μ‘ 속도와 λΆ€λ“œλŸ¬μ›€ 졜우μ„