RISC-V Emulator

A lightweight RISC-V emulator written in C++, developed as a class project to simulate the RISC-V 32IM instruction set architecture (ISA).
The emulator supports 32-bit integer, multiplication, and division instructions, and is capable of loading and executing ELF binaries.

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Features

• Implements the RISC-V 32IM ISA (RV32I + multiplication/division).
• Three-stage pipeline: Fetch → Decode → Execute.
• Register file with 32 registers (including PC and SP).
• ALU for arithmetic and logic operations.
• DRAM model for instruction and data storage.
• ELF loader that:
  • Parses 32-bit RISC-V ELF executables.
  • Loads program sections into DRAM.
  • Sets the entry point for execution.

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Project Structure

RISC-V/ ├── Header Files/ │ ├── ALU.h │ ├── Bus.h │ ├── Constants.h │ ├── Decoder.h │ ├── DRAM.h │ ├── ELFLoader.h │ ├── Machine.h │ └── Register.h │ ├── Source Files/ │ ├── ALU.cpp │ ├── Bus.cpp │ ├── Decoder.cpp │ ├── DRAM.cpp │ ├── ELFLoader.cpp │ ├── Machine.cpp │ ├── Register.cpp │ └── main.cpp

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Building

Make sure you have a modern C++ compiler (C++17 or later).

# Compile key source files
 -g++ -std=c++17 ALU.cpp Bus.cpp Decoder.cpp DRAM.cpp ELFLoader.cpp Machine.cpp Register.cpp main.cpp -o riscv-emulator