Bug fix: shuffled array assignments incorrectly collapsed in generated SV #504
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Description & Motivation
The checks for collapsing array assignments in generated SystemVerilog had checked that all elements from one array are assigned to all elements of another array. However, it did not check that the order on the driver matched the order on the receiver. This means if you did all elements from one array to all elements of another array, but shuffled the order, the assignments would be incorrectly collapsed and the generated SV would be incorrect.
This PR introduces a fix for this bug and adds a test which failed prior to the fix, but now passes.
Related Issue(s)
N/A
Testing
Added new test
Backwards-compatibility
No
Documentation
No