[Docs] Fixed typo in VerilogGeneration.md (#6394)

Fixed typo in VerilogGeneration.md
llvm · Nov 8, 2023 · 1ea76ba · 1ea76ba
1 parent e49b521
commit 1ea76ba
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/docs/VerilogGeneration.md b/docs/VerilogGeneration.md
@@ -61,7 +61,7 @@ this case, what length of lines the emitter should aim for (e.g. 80 columns
 wide, 120 wide, etc), and whether the emitter is allowed to use `automatic
 logic` declarations in nested blocks or not.
 
-The defaults in `LoweringOptions` are set up to generate aethetically pleasing
+The defaults in `LoweringOptions` are set up to generate aesthetically pleasing
 output, and to use the modern features of SystemVerilog where possible.  Client
 tools and frontends can change these, e.g. if they need to generate standard
 Verilog for older tools.