[FIRRTL] Fix isX lowering for aggregates

Oversight in lowering. bitcast to an int to do the check. Closes #6926
llvm · May 1, 2024 · acbee5d · acbee5d
1 parent b2ae5cf
commit acbee5d
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Showing 2 changed files with 25 additions and 1 deletion.
diff --git a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp
@@ -3648,6 +3648,14 @@ LogicalResult FIRRTLLowering::visitExpr(IsXIntrinsicOp op) {
   if (!input)
     return failure();
 
+  if (!isa<IntType>(input.getType())) {
+    auto srcType = op.getArg().getType();
+    auto bitwidth = firrtl::getBitWidth(type_cast<FIRRTLBaseType>(srcType));
+    assert(bitwidth && "Unknown width");
+    auto intType = builder.getIntegerType(*bitwidth);
+    input = builder.createOrFold<hw::BitcastOp>(intType, input);
+  }
+
   return setLoweringTo<comb::ICmpOp>(
       op, ICmpPredicate::ceq, input,
       getOrCreateXConstant(input.getType().getIntOrFloatBitWidth()), true);

diff --git a/test/Conversion/FIRRTLToHW/intrinsics.mlir b/test/Conversion/FIRRTLToHW/intrinsics.mlir
@@ -2,7 +2,10 @@
 
 firrtl.circuit "Intrinsics" {
   // CHECK-LABEL: hw.module @Intrinsics
-  firrtl.module @Intrinsics(in %clk: !firrtl.clock, in %a: !firrtl.uint<1>) {
+  firrtl.module @Intrinsics(in %clk: !firrtl.clock, in %a: !firrtl.uint<1>,
+                            in %b: !firrtl.vector<uint<2>, 3>,
+                            in %c: !firrtl.bundle<a: uint<3>, b: uint<3>>) {
+    // CHECK-NEXT: %x_i6 = sv.constantX : i6
     // CHECK-NEXT: [[CLK:%.+]] = seq.from_clock %clk
     // CHECK-NEXT: %x_i1 = sv.constantX : i1
     // CHECK-NEXT: [[T0:%.+]] = comb.icmp bin ceq %a, %x_i1
@@ -24,6 +27,19 @@ firrtl.circuit "Intrinsics" {
     %x2 = firrtl.node interesting_name %2 : !firrtl.uint<1>
     %x3 = firrtl.node interesting_name %3 : !firrtl.uint<1>
     %x4 = firrtl.node interesting_name %4 : !firrtl.uint<5>
+
+    // CHECK-NEXT: %[[vecCast:.*]] = hw.bitcast %b
+    // CHECK-NEXT: comb.icmp bin ceq %[[vecCast]], %x_i6
+    // CHECK-NEXT: %x5 = hw.wire
+    %5 = firrtl.int.isX %b : !firrtl.vector<uint<2>,3>
+    %x5 = firrtl.node interesting_name %5 : !firrtl.uint<1>
+
+    // CHECK-NEXT: %[[bundleCast:.*]] = hw.bitcast %c
+    // CHECK-NEXT: comb.icmp bin ceq %[[bundleCast]], %x_i6
+    // CHECK-NEXT: %x6 = hw.wire
+    %6 = firrtl.int.isX %c : !firrtl.bundle<a: uint<3>, b: uint<3>>
+    %x6 = firrtl.node interesting_name %6 : !firrtl.uint<1>
+
   }
 
   // CHECK-LABEL: hw.module @ClockGate