Merge branch 'main' into teqdruid/rm-esicollat

lib/Conversion/ExportVerilog/ExportVerilog.cpp

@@ -6052,10 +6052,8 @@ void FileEmitter::emit(emit::FileOp op) {
         .Case<emit::VerbatimOp>([&](auto op) { emitOp(op); })
         .Case<VerbatimOp, IfDefOp, MacroDefOp>(
             [&](auto op) { ModuleEmitter(state).emitStatement(op); })
-        .Default([&](auto op) {
-          op->emitError("cannot be emitted to a file");
-          state.encounteredError = true;
-        });
+        .Default(
+            [&](auto op) { emitOpError(op, "cannot be emitted to a file"); });
   }
   ps.eof();
 }
@@ -6067,8 +6065,7 @@ void FileEmitter::emit(emit::FileListOp op) {
 
     auto it = state.fileMapping.find(fileName);
     if (it == state.fileMapping.end()) {
-      op->emitError() << " references an invalid file: " << sym;
-      state.encounteredError = true;
+      emitOpError(op, " references an invalid file: ") << sym;
       continue;
     }
 

lib/Dialect/ESI/runtime/cosim/cosim_dpi_server/CMakeLists.txt

@@ -18,7 +18,7 @@ set_target_properties(EsiCosimDpiServer
 add_dependencies(EsiCosimDpiServer EsiCosimCapnp MtiPli)
 target_link_libraries(EsiCosimDpiServer PRIVATE EsiCosimCapnp MtiPli)
 install(TARGETS EsiCosimDpiServer
-  DESTINATION cosim
+  DESTINATION lib
   COMPONENT ESIRuntime
 )
 

lib/Dialect/ESI/runtime/cosim/esi-cosim.py

@@ -23,7 +23,7 @@
 import sys
 import textwrap
 import time
-from typing import List
+from typing import Dict, List
 
 _thisdir = Path(__file__).parent
 CosimCollateralDir = _thisdir.parent / "cosim"
@@ -64,7 +64,7 @@ def dpi_so_paths(self) -> List[Path]:
     """Return a list of all the DPI shared object files."""
 
     def find_so(name: str) -> Path:
-      for path in os.environ["LD_LIBRARY_PATH"].split(":"):
+      for path in Simulator.get_env().get("LD_LIBRARY_PATH", "").split(":"):
         if os.name == "nt":
           so = Path(path) / f"{name}.dll"
         else:
@@ -93,12 +93,26 @@ def __init__(self, sources: SourceFiles, run_dir: Path, debug: bool):
     self.run_dir = run_dir
     self.debug = debug
 
+  @staticmethod
+  def get_env() -> Dict[str, str]:
+    """Get the environment variables to locate shared objects."""
+
+    env = os.environ.copy()
+    env["LIBRARY_PATH"] = env.get("LIBRARY_PATH", "") + ":" + str(
+        _thisdir.parent / "lib")
+    env["LD_LIBRARY_PATH"] = env.get("LD_LIBRARY_PATH", "") + ":" + str(
+        _thisdir.parent / "lib")
+    return env
+
   def compile_command(self) -> List[str]:
     """Compile the sources. Returns the exit code of the simulation compiler."""
     assert False, "Must be implemented by subclass"
 
   def compile(self) -> int:
-    cp = subprocess.run(self.compile_command(), capture_output=True, text=True)
+    cp = subprocess.run(self.compile_command(),
+                        env=Simulator.get_env(),
+                        capture_output=True,
+                        text=True)
     self.run_dir.mkdir(parents=True, exist_ok=True)
     open(self.run_dir / "compile_stdout.log", "w").write(cp.stdout)
     open(self.run_dir / "compile_stderr.log", "w").write(cp.stderr)
@@ -134,7 +148,7 @@ def run(self, inner_command: str) -> int:
         os.remove(portFileName)
 
       # Run the simulation.
-      simEnv = os.environ.copy()
+      simEnv = Simulator.get_env()
       if self.debug:
         simEnv["COSIM_DEBUG_FILE"] = "cosim_debug.log"
       simProc = subprocess.Popen(self.run_command(),
@@ -174,7 +188,7 @@ def run(self, inner_command: str) -> int:
         time.sleep(0.05)
 
       # Run the inner command, passing the connection info via environment vars.
-      testEnv = os.environ.copy()
+      testEnv = Simulator.get_env()
       testEnv["ESI_COSIM_PORT"] = str(port)
       testEnv["ESI_COSIM_HOST"] = "localhost"
       return subprocess.run(inner_command, cwd=os.getcwd(),

test/Conversion/FIRRTLToHW/lower-to-hw.mlir

@@ -1586,12 +1586,12 @@ firrtl.circuit "Directories" attributes {
   ]
 } {
   // CHECK-LABEL: hw.module private @Directories_A
-  // CHECK-SAME:    output_file = #hw.output_file<"hello/"
+  // CHECK-SAME:    output_file = #hw.output_file<"hello{{/|\\\\}}"
   firrtl.module private @Directories_A() attributes {
     output_file = #hw.output_file<"hello/", excludeFromFileList>
   } {}
   // CHECK:       hw.module private @BoundUnderDUT
-  // CHECK-SAME:    output_file = #hw.output_file<"testbench/"
+  // CHECK-SAME:    output_file = #hw.output_file<"testbench{{/|\\\\}}"
   firrtl.module private @BoundUnderDUT() {}
   firrtl.module private @DUT() attributes {
     annotations = [

test/Dialect/FIRRTL/lower-layers.mlir

@@ -613,12 +613,12 @@ firrtl.circuit "Foo" attributes {
 // CHECK-LABEL: firrtl.circuit "Foo"
 //
 // CHECK:       sv.verbatim
-// CHECK-SAME:    #hw.output_file<"testbench{{[/\]}}layers_Foo_A.sv", excludeFromFileList>
+// CHECK-SAME:    #hw.output_file<"testbench{{/|\\\\}}layers_Foo_A.sv", excludeFromFileList>
 //
 // CHECK:       firrtl.module {{.*}} @Bar_A
-// CHECK-SAME:    #hw.output_file<"testbench{{[/\]}}", excludeFromFileList>
+// CHECK-SAME:    #hw.output_file<"testbench{{/|\\\\}}", excludeFromFileList>
 // CHECK:       firrtl.module {{.*}} @Foo_A
-// CHECK-SAME:    #hw.output_file<"testbench{{[/\]}}", excludeFromFileList>
+// CHECK-SAME:    #hw.output_file<"testbench{{/|\\\\}}", excludeFromFileList>
 //
 // CHECK:       sv.verbatim
-// CHECK-SAME:    #hw.output_file<"testbench{{[/\]}}layers_Foo_A.sv", excludeFromFileList>
+// CHECK-SAME:    #hw.output_file<"testbench{{/|\\\\}}layers_Foo_A.sv", excludeFromFileList>

tools/hlstool/hlstool.cpp

@@ -12,7 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/Passes.h"
+#include "mlir/Conversion/AffineToStandard/AffineToStandard.h"
+#include "mlir/Conversion/SCFToControlFlow/SCFToControlFlow.h"
 #include "mlir/Dialect/Affine/IR/AffineOps.h"
 #include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"