[Verif] Add StripContracts pass #8144
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| getOperation()->walk([](ContractOp op) { | ||
| op.replaceAllUsesWith(op.getInputs()); | ||
| op.erase(); | ||
| }); |
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Pretty degenerate case but does this work in the following case?
%0 = verif.contract %1 : i32 {}
%1 = verif.contract %0 : i32 {}
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Good thinking. Should work. Let me add this to the tests.
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Actually needed a tweak to avoid an assert in replaceAllUsesWith and to allow op.erase to work if the operation is cycle.
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| hw.module @bar() { | ||
| // CHECK-NOT: verif.contract | ||
| %0 = verif.contract %1 : i42 {} | ||
| %1 = verif.contract %0 : i42 {} |
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What's actually the semantics if we return %1 as an output of the module? Also, the pass would still crash in that case, right? Not really important to fix here though. We have similar issues with comb.
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That's a great point, that would still crash. It would be better if it didn't, though. I think in that case we'd want to just not remove the contract. But the semantics are the same as in %0 = comb.add %0, %0; hw.output %0 -- hard to define. Maybe some undefined or poison value, or unknown.
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Fixed this for now by just not removing cyclical contracts.
Add a simple pass that removes all contracts from the IR, treating them as passthroughs. Run the pass in firtool's HW-to-SV pipeline early on to add additional optimization opportunities. ExportVerilog will eventually ignore contracts anyway.
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Add a simple pass that removes all contracts from the IR, treating them as passthroughs. Run the pass in firtool's HW-to-SV pipeline early on to add additional optimization opportunities. ExportVerilog will eventually ignore contracts anyway.