[Arcilator] Allow running verif.simulation ops #8233
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fabianschuiki
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| %failure = seq.compreg %6, %clock reset %init, %false : i1 | ||
| %6 = comb.or %failure, %5 : i1 | ||
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| // Print some statistics about the test. |
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| SmallVector<StringAttr> symbols; | ||
| getOperation().walk([&](verif::SimulationOp op) { | ||
| auto *symbolTableOp = SymbolTable::getNearestSymbolTable(op); |
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Is there a need to have verif.simulation nested in arbitrary ops or could we require builtin.module as parent to simplify this?
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That would definitely be an option! I wasn't entirely sure though if we support HWModules nested in other operations – I think we might, for stuff like sv.ifdef and similar. But we could definitely just force the verif.* tests to be in a builtin.module.
| // Compute `exit_code | (exit_code != 0)` as a way of guaranteeing that | ||
| // the exit code will be non-zero even if bits are truncated by the operating | ||
| // system. |
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Smart way to deal with the fact that exit typically ANDs with 0xFF. Maybe worth mentioning in the simulation op documentation that on non-zero exit code the least significant bit is always set? But I guess also not really, because we are very vague about that anyway.
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Yeah I'm less and less convinced that we should actually have a multi-bit exit code at all. Maybe a success line would be better…
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fabianschuiki
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Add the `LowerVerifSimulations` pass to the Arc dialect. This pass converts any `verif.simulation` ops in the input into a test harness module and a `func.func` that instantiates the module and applies the necessary stimulus to it using `arc.sim.*` ops. Also add the pass to the arcilator pipeline. This allows the user to run any `verif.simulation` ops in the input design by specifying the `--run --jit-entry=<simulation-name>` command line options. We may want to streamline this in the future. Also add an integration test which verifies an adder circuit and prints the simulation results.
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Add the
LowerVerifSimulationspass to the Arc dialect. This pass converts anyverif.simulationops in the input into a test harness module and afunc.functhat instantiates the module and applies the necessary stimulus to it usingarc.sim.*ops.Also add the pass to the arcilator pipeline. This allows the user to run any
verif.simulationops in the input design by specifying the--run --jit-entry=<simulation-name>command line options. We may want to streamline this in the future.Also add an integration test which verifies an adder circuit and prints the simulation results.