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@lerwys
lerwys committed Jul 9, 2020
2 parents 31d42c1 + c1928d5 commit f411b6b
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Showing 265 changed files with 327 additions and 251,717 deletions.
10 changes: 0 additions & 10 deletions hdl/modules/Manifest.py
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Original file line number Diff line number Diff line change
@@ -1,10 +1,6 @@
files = [ "dsp_cores_pkg.vhd" ];

modules = { "local" : [
"position_calc",
"wb_position_calc",
"wb_bpm_swap",
"sw_windowing",
"multiplier",
"pipeline",
"ce_synch",
Expand All @@ -13,16 +9,10 @@
"cordic",
"cordic_iter",
"divider",
"fixed_dds",
"mixer",
"downconv",
"delta_sigma",
"pipeline",
"input_gen",
"strobe_gen",
"clock_driver",
"machine",
"rp_math_pack",
"part_delta_sigma",
"hpf_adcinput"
] };
279 changes: 55 additions & 224 deletions hdl/modules/cic/cic_dyn.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,7 @@ end entity cic_dyn;
architecture str of cic_dyn is

signal decimation_strobe : std_logic := '0';
signal decimation_strobe_d0 : std_logic := '0';
signal data_out : std_logic_vector(g_output_width-1 downto 0) := (others => '0');
signal valid_out : std_logic := '0';
signal synch_int : std_logic := '0';
Expand All @@ -81,24 +82,13 @@ architecture str of cic_dyn is
type t_fsm_cic_sync_state is (IDLE, CHECK_SYNC, START_SYNC, SYNCHING);
signal fsm_cic_sync_current_state : t_fsm_cic_sync_state := IDLE;

type t_fsm_data_mask_state is (IDLE, CHECK_TRANSITION, MASKING_BEG, PASSTHROUGH, MASKING_END);
signal fsm_data_mask_current_state : t_fsm_data_mask_state := IDLE;

signal data_mask_beg_counter : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_beg_counter_max : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_beg_bypass : std_logic := '0';
signal data_mask_end_counter : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_end_counter_max : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_end_bypass : std_logic := '0';
signal data_mask_pt_counter : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_pt_counter_max : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_pt_bypass : std_logic := '0';
signal data_mask_en_d0 : std_logic := '0';
signal data_mask_beg_idx : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_end_idx : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_counter : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);

signal valid_d0 : std_logic := '0';
signal data_d0 : std_logic_vector(g_input_width-1 downto 0) := (others => '0');
Expand Down Expand Up @@ -131,232 +121,66 @@ begin -- architecture str
p_data_mask_limits : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_mask_beg_counter_max <= to_unsigned(0, data_mask_beg_counter_max'length);
data_mask_beg_bypass <= '0';
data_mask_end_counter_max <= to_unsigned(0, data_mask_end_counter_max'length);
data_mask_end_bypass <= '0';
data_mask_pt_counter_max <= to_unsigned(g_max_rate, data_mask_pt_counter_max'length);
data_mask_pt_bypass <= '0';
if rst_i = '1' then
data_mask_beg_idx <= (others => '0');
data_mask_end_idx <= (others => '0');
else
-- Set state counters
if data_mask_num_samples_beg_i > to_unsigned(0, data_mask_num_samples_beg_i'length) then
data_mask_beg_counter_max <= data_mask_num_samples_beg_i - 1;
data_mask_beg_bypass <= '0';
else
data_mask_beg_counter_max <= to_unsigned(0, data_mask_num_samples_beg_i'length);
data_mask_beg_bypass <= '1';
end if;

if data_mask_num_samples_end_i > to_unsigned(0, data_mask_num_samples_end_i'length) then
data_mask_end_counter_max <= data_mask_num_samples_end_i - 1;
data_mask_end_bypass <= '0';
else
data_mask_end_counter_max <= to_unsigned(0, data_mask_num_samples_end_i'length);
data_mask_end_bypass <= '1';
-- Set beginning counter index
data_mask_beg_idx <= data_mask_num_samples_beg_i;
if data_mask_num_samples_beg_i > g_max_rate then
data_mask_beg_idx <= to_unsigned(g_max_rate, data_mask_beg_idx'length);
end if;

if (g_max_rate >
data_mask_num_samples_beg_i + data_mask_num_samples_end_i) then
data_mask_pt_counter_max <= g_max_rate -
data_mask_num_samples_beg_i -
data_mask_num_samples_end_i - 1;
data_mask_pt_bypass <= '0';
else
data_mask_pt_counter_max <= to_unsigned(0, data_mask_pt_counter_max'length);
data_mask_pt_bypass <= '1';
-- Set ending counter index
data_mask_end_idx <= g_max_rate - data_mask_num_samples_end_i;
if data_mask_num_samples_end_i > g_max_rate then
data_mask_end_idx <= to_unsigned(0, data_mask_end_idx'length);
end if;
end if;
end if;
end process;

p_data_mask_fsm : process(clk_i)
-- Data masking logic
p_data_mask : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
fsm_data_mask_current_state <= IDLE;
if rst_i = '1' then
data_mask_counter <= (others => '0');
valid_d0 <= '0';
data_d0 <= (others => '0');
data_tag_d0 <= (others => '0');
data_tag_d1 <= (others => '0');
data_mask_beg_counter <= to_unsigned(0, data_mask_beg_counter'length);
data_mask_end_counter <= to_unsigned(0, data_mask_end_counter'length);
data_mask_pt_counter <= to_unsigned(0, data_mask_pt_counter'length);
data_mask_en_d0 <= '0';
else
if ce_i = '1' then

-- We take one clock cycle to detect a transition and act on it.
-- so, delay everyone by this same amount
valid_d0 <= valid_i;
data_d0 <= data_i;

-- tags are only valid if valid_i = '1'
if valid_i = '1' then
data_tag_d0 <= data_tag_i;
-- To check for a transition we need another clock cycle. So, use a
-- delayed version of data_tag
data_tag_d1 <= data_tag_d0;
end if;

-- FSM transitions
case fsm_data_mask_current_state is
when IDLE =>
-- passthrough
valid_d0 <= valid_i;
data_mask_counter <= data_mask_counter + 1;

-- decimation_strobe always happens at g_max_rate clock
-- cycles
if decimation_strobe = '1' then
data_mask_counter <= (others => '0');
data_mask_en_d0 <= data_mask_en_i;
end if;

if data_mask_en_d0 = '1' and
(data_mask_counter < data_mask_beg_idx or
data_mask_counter >= data_mask_end_idx) then
data_d0 <= (others => '0');
else
data_d0 <= data_i;
end if;
end if;

if data_mask_en_i = '0' then
fsm_data_mask_current_state <= IDLE;
else
fsm_data_mask_current_state <= CHECK_TRANSITION;
end if;

when CHECK_TRANSITION =>
-- data mask is disabled
if data_mask_en_i = '0' then
fsm_data_mask_current_state <= IDLE;
else
-- wait for tag transition
if decimation_strobe = '1' then
-- mask input samples up to a max
if valid_i = '1' then

fsm_data_mask_current_state <= CHECK_TRANSITION;

-- data to mask at the beginning
if data_mask_beg_bypass = '0' then
data_d0 <= (others => '0');
data_mask_beg_counter <= to_unsigned(0, data_mask_beg_counter'length);
fsm_data_mask_current_state <= MASKING_BEG;
elsif data_mask_pt_bypass = '0' then
data_mask_pt_counter <= to_unsigned(0, data_mask_pt_counter'length);
fsm_data_mask_current_state <= PASSTHROUGH;
elsif data_mask_end_bypass = '0' then
data_d0 <= (others => '0');
data_mask_end_counter <= to_unsigned(0, data_mask_end_counter'length);
fsm_data_mask_current_state <= MASKING_END;
end if;

end if;
end if;
end if;

when MASKING_BEG =>
-- data mask is disabled
if data_mask_en_i = '0' then
fsm_data_mask_current_state <= IDLE;
else

if valid_i = '1' then
data_mask_beg_counter <= data_mask_beg_counter + 1;
end if;

if data_mask_beg_counter = data_mask_beg_counter_max then
-- data to mask at the beginning
if data_mask_pt_bypass = '0' then
data_mask_pt_counter <= to_unsigned(0, data_mask_pt_counter'length);
fsm_data_mask_current_state <= PASSTHROUGH;
elsif data_mask_end_bypass = '0' then
data_d0 <= (others => '0');
data_mask_end_counter <= to_unsigned(0, data_mask_end_counter'length);
fsm_data_mask_current_state <= MASKING_END;
else
fsm_data_mask_current_state <= CHECK_TRANSITION;

-- No time to check the transition at the CHECK_TRANSITION
-- state. Change now
if decimation_strobe = '1' and valid_i = '1' then
if data_mask_beg_bypass = '0' then
data_d0 <= (others => '0');
data_mask_beg_counter <= to_unsigned(0, data_mask_beg_counter'length);
fsm_data_mask_current_state <= MASKING_BEG;
end if;
end if;

end if;
end if;
end if;

when PASSTHROUGH =>
-- data mask is disabled
if data_mask_en_i = '0' then
fsm_data_mask_current_state <= IDLE;
else

if valid_i = '1' then
data_mask_pt_counter <= data_mask_pt_counter + 1;
end if;

if data_mask_pt_counter = data_mask_pt_counter_max then
-- data to mask at the beginning
if data_mask_end_bypass = '0' then
data_d0 <= (others => '0');
data_mask_end_counter <= to_unsigned(0, data_mask_end_counter'length);
fsm_data_mask_current_state <= MASKING_END;
else
fsm_data_mask_current_state <= CHECK_TRANSITION;

-- No time to check the transition at the CHECK_TRANSITION
-- state. Change now
if decimation_strobe = '1' and valid_i = '1' then
if data_mask_beg_bypass = '0' then
data_d0 <= (others => '0');
data_mask_beg_counter <= to_unsigned(0, data_mask_beg_counter'length);
fsm_data_mask_current_state <= MASKING_BEG;
elsif data_mask_pt_bypass = '0' then
data_mask_pt_counter <= to_unsigned(0, data_mask_pt_counter'length);
fsm_data_mask_current_state <= PASSTHROUGH;
end if;
end if;

end if;
end if;
end if;

when MASKING_END =>
-- data mask is disabled
if data_mask_en_i = '0' then
fsm_data_mask_current_state <= IDLE;
else

if valid_i = '1' then
data_mask_end_counter <= data_mask_end_counter + 1;
end if;

if data_mask_end_counter = data_mask_end_counter_max then
fsm_data_mask_current_state <= CHECK_TRANSITION;

-- No time to check the transition at the CHECK_TRANSITION
-- state. Change now
if decimation_strobe = '1' and valid_i = '1' then
if data_mask_beg_bypass = '0' then
data_d0 <= (others => '0');
data_mask_beg_counter <= to_unsigned(0, data_mask_beg_counter'length);
fsm_data_mask_current_state <= MASKING_BEG;
elsif data_mask_pt_bypass = '0' then
data_mask_pt_counter <= to_unsigned(0, data_mask_pt_counter'length);
fsm_data_mask_current_state <= PASSTHROUGH;
elsif data_mask_end_bypass = '0' then
data_d0 <= (others => '0');
data_mask_end_counter <= to_unsigned(0, data_mask_end_counter'length);
fsm_data_mask_current_state <= MASKING_END;
end if;
end if;

end if;
end if;

when others =>
fsm_data_mask_current_state <= IDLE;

end case;
-- We take one clock cycle to detect a transition and act on it.
-- so, delay everyone by this same amount
valid_d0 <= valid_i;
decimation_strobe_d0 <= decimation_strobe;

end if;
end if;
end if;
end process;

data_tag_change <= '1' when valid_i = '1' and data_tag_i /= data_tag_d0 else '0';
data_tag_change <= '1' when data_tag_i /= data_tag_d0 else '0';
data_tag_change_d0 <= '1' when data_tag_d0 /= data_tag_d1 else '0';

p_sync_cic_fsm : process(clk_i)
Expand All @@ -365,13 +189,20 @@ begin -- architecture str
if rst_i = '1' then
fsm_cic_sync_current_state <= IDLE;
rst_modules <= '0';
desync_cnt <= to_unsigned(0, desync_cnt'length);
desync_cnt <= (others => '0');
data_tag_d0 <= (others => '0');
data_tag_d1 <= (others => '0');
else
if ce_i = '1' then

data_tag_d0 <= data_tag_i;
-- To check for a transition we need another clock cycle. So, use a
-- delayed version of data_tag
data_tag_d1 <= data_tag_d0;

-- Desync clear
if data_tag_desync_cnt_rst_i = '1' then
desync_cnt <= to_unsigned(0, desync_cnt'length);
desync_cnt <= (others => '0');
end if;

-- FSM transitions
Expand Down Expand Up @@ -467,7 +298,7 @@ begin -- architecture str
data_i => data_d0,
data_o => data_out,
act_i => valid_d0,
act_out_i => decimation_strobe,
act_out_i => decimation_strobe_d0,
val_o => valid_out);

gen_with_ce_sync : if g_with_ce_synch generate
Expand Down
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