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@meiniKi
meiniKi committed Jan 3, 2022
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21 changes: 20 additions & 1 deletion README.md
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Expand Up @@ -26,4 +26,23 @@ cd scripts
## Dev
install ```sigrok-firmware-fx2lafw```

https://sigrok.org/wiki/Linux
https://sigrok.org/wiki/Linux


# Modules

- Module: [core ](./doc/doc_internal/core.md)
- Module: [ctrl ](./doc/doc_internal/ctrl.md)
- Module: [indec ](./doc/doc_internal/indec.md)
- Module: [logIP ](./doc/doc_internal/logIP.md)
- Module: [logIP_pkg ](./doc/doc_internal/logIP_pkg.md)
- Module: [lutram ](./doc/doc_internal/lutram.md)
- Module: [ramif ](./doc/doc_internal/ramif.md)
- Module: [rdback ](./doc/doc_internal/rdback.md)
- Module: [sampler ](./doc/doc_internal/sampler.md)
- Module: [stage ](./doc/doc_internal/stage.md)
- Module: [syncro ](./doc/doc_internal/syncro.md)
- Module: [trigger ](./doc/doc_internal/trigger.md)
- Module: [tuart_rx ](./doc/doc_internal/tuart_rx.md)
- Module: [tuart_tx ](./doc/doc_internal/tuart_tx.md)

113 changes: 52 additions & 61 deletions demo/basys3/out/post_route_timing_summary.rpt
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40 changes: 20 additions & 20 deletions demo/basys3/out/post_route_util.rpt
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Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Jan 3 11:41:05 2022
| Date : Mon Jan 3 13:23:32 2022
| Host : user-ThinkPad-T480 running 64-bit Ubuntu 20.04.3 LTS
| Command : report_utilization -file ../out/post_route_util.rpt
| Design : top
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| LUT as Memory | 512 | 0 | 0 | 9600 | 5.33 |
| LUT as Distributed RAM | 512 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 874 | 0 | 0 | 41600 | 2.10 |
| Register as Flip Flop | 874 | 0 | 0 | 41600 | 2.10 |
| Slice Registers | 873 | 0 | 0 | 41600 | 2.10 |
| Register as Flip Flop | 873 | 0 | 0 | 41600 | 2.10 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 272 | 0 | 0 | 16300 | 1.67 |
| F8 Muxes | 128 | 0 | 0 | 8150 | 1.57 |
Expand All @@ -60,7 +60,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 13 | Yes | Set | - |
| 861 | Yes | Reset | - |
| 860 | Yes | Reset | - |
+-------+--------------+-------------+--------------+


Expand All @@ -70,24 +70,24 @@ Table of Contents
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
| Slice | 403 | 0 | 0 | 8150 | 4.94 |
| SLICEL | 210 | 0 | | | |
| SLICEM | 193 | 0 | | | |
| Slice | 397 | 0 | 0 | 8150 | 4.87 |
| SLICEL | 213 | 0 | | | |
| SLICEM | 184 | 0 | | | |
| LUT as Logic | 551 | 0 | 0 | 20800 | 2.65 |
| using O5 output only | 0 | | | | |
| using O6 output only | 441 | | | | |
| using O5 and O6 | 110 | | | | |
| using O6 output only | 444 | | | | |
| using O5 and O6 | 107 | | | | |
| LUT as Memory | 512 | 0 | 0 | 9600 | 5.33 |
| LUT as Distributed RAM | 512 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 512 | | | | |
| using O5 and O6 | 0 | | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 874 | 0 | 0 | 41600 | 2.10 |
| Register driven from within the Slice | 336 | | | | |
| Register driven from outside the Slice | 538 | | | | |
| LUT in front of the register is unused | 357 | | | | |
| LUT in front of the register is used | 181 | | | | |
| Slice Registers | 873 | 0 | 0 | 41600 | 2.10 |
| Register driven from within the Slice | 321 | | | | |
| Register driven from outside the Slice | 552 | | | | |
| LUT in front of the register is unused | 333 | | | | |
| LUT in front of the register is used | 219 | | | | |
| Unique Control Sets | 34 | | 0 | 8150 | 0.42 |
+--------------------------------------------+------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
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+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 861 | Flop & Latch |
| FDRE | 860 | Flop & Latch |
| RAMS64E | 512 | Distributed Memory |
| MUXF7 | 272 | MuxFx |
| LUT6 | 232 | LUT |
| LUT5 | 176 | LUT |
| LUT6 | 244 | LUT |
| LUT5 | 165 | LUT |
| MUXF8 | 128 | MuxFx |
| LUT2 | 117 | LUT |
| LUT4 | 93 | LUT |
| LUT2 | 118 | LUT |
| LUT4 | 89 | LUT |
| CARRY4 | 60 | CarryLogic |
| LUT3 | 22 | LUT |
| LUT3 | 21 | LUT |
| LUT1 | 21 | LUT |
| FDSE | 13 | Flop & Latch |
| OBUF | 3 | IO |
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