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Improvements for riscv #65

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merged 4 commits into from
Dec 26, 2024
Merged

Improvements for riscv #65

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07c52c4
boards/esp32c3-legacy: Add missing include to esp32c3_boot.c
no1wudi Nov 11, 2024
2ff5427
riscv: Suppress LOAD RWX linker warning
no1wudi Nov 11, 2024
33e8e9f
arch/risc-v: Add ARCH_HAVE_RAMFUNCS option for ESP32-C3
no1wudi Nov 12, 2024
6ef6b5e
risc-v: Move CSR register manipulation macros to csr.h
no1wudi Dec 9, 2024
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2 changes: 2 additions & 0 deletions arch/risc-v/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,7 @@ config ARCH_CHIP_ESP32C3
select ARCH_HAVE_BOOTLOADER
select ARCH_HAVE_PERF_EVENTS
select ARCH_HAVE_DEBUG
select ARCH_HAVE_RAMFUNCS
---help---
Espressif ESP32-C3 (RV32IMC).

Expand Down Expand Up @@ -119,6 +120,7 @@ config ARCH_CHIP_ESP32C3_GENERIC
select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
select ARCH_CHIP_ESPRESSIF
select ARCH_HAVE_DEBUG
select ARCH_HAVE_RAMFUNCS
---help---
ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory

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85 changes: 85 additions & 0 deletions arch/risc-v/include/csr.h
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Expand Up @@ -734,6 +734,91 @@
#define ISELECT_EIE62 0xfe
#define ISELECT_EIE63 0xff

#ifndef __ASSEMBLY__

/* Read the value of a CSR register */

#define READ_CSR(reg) \
({ \
uintreg_t __regval; \
__asm__ __volatile__("csrr %0, " __STR(reg) : "=r"(__regval)); \
__regval; \
})

/* Read the value of a CSR register and set the specified bits */

#define READ_AND_SET_CSR(reg, bits) \
({ \
uintreg_t __regval; \
__asm__ __volatile__("csrrs %0, " __STR(reg) ", %1": "=r"(__regval) : "rK"(bits)); \
__regval; \
})

/* Write a value to a CSR register */

#define WRITE_CSR(reg, val) \
({ \
__asm__ __volatile__("csrw " __STR(reg) ", %0" :: "rK"(val)); \
})

/* Set the specified bits in a CSR register */

#define SET_CSR(reg, bits) \
({ \
__asm__ __volatile__("csrs " __STR(reg) ", %0" :: "rK"(bits)); \
})

/* Clear the specified bits in a CSR register */

#define CLEAR_CSR(reg, bits) \
({ \
__asm__ __volatile__("csrc " __STR(reg) ", %0" :: "rK"(bits)); \
})

/* Swap the value of a CSR register with the specified value */

#define SWAP_CSR(reg, val) \
({ \
uintptr_t regval; \
__asm__ __volatile__("csrrw %0, " __STR(reg) ", %1" : "=r"(regval) \
: "rK"(val)); \
regval; \
})

/* Write a value to an indirect CSR register */

#define WRITE_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
WRITE_CSR(CSR_IREG, val); \
})

/* Read the value of an indirect CSR register */

#define READ_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
READ_CSR(CSR_IREG, val); \
})

/* Set the specified bits in an indirect CSR register */

#define SET_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
SET_CSR(CSR_IREG, val); \
})

/* Clear the specified bits in an indirect CSR register */

#define CLEAR_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
CLEAR_CSR(CSR_IREG, val); \
})

#endif /* __ASSEMBLY__ */

/****************************************************************************
* Public Types
****************************************************************************/
Expand Down
6 changes: 6 additions & 0 deletions arch/risc-v/src/cmake/Toolchain.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -265,6 +265,12 @@ if(CONFIG_RISCV_TOOLCHAIN STREQUAL GNU_RVG)
string(REGEX MATCH "([0-9]+)\\.[0-9]+" GCC_VERSION_REGEX
"${GCC_VERSION_OUTPUT}")
set(GCCVER ${CMAKE_MATCH_1})

if(GCCVER GREATER_EQUAL 12)
if(CONFIG_ARCH_RAMFUNCS OR NOT CONFIG_BOOT_RUNFROMFLASH)
add_link_options(-Wl,--no-warn-rwx-segments)
endif()
endif()
endif()

if(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI)
Expand Down
7 changes: 7 additions & 0 deletions arch/risc-v/src/common/Toolchain.defs
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Original file line number Diff line number Diff line change
Expand Up @@ -386,6 +386,13 @@ ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
ifeq ($(GCCVER),)
export GCCVER := $(shell $(CC) --version | grep gcc | sed -E "s/.* ([0-9]+\.[0-9]+).*/\1/" | cut -d'.' -f1)
endif
ifeq ($(shell expr "$(GCCVER)" \>= 12), 1)
ifeq ($(CONFIG_ARCH_RAMFUNCS),y)
LDFLAGS += --no-warn-rwx-segments
else ifeq ($(CONFIG_BOOT_RUNFROMFLASH),)
LDFLAGS += --no-warn-rwx-segments
endif
endif
endif
endif

Expand Down
61 changes: 0 additions & 61 deletions arch/risc-v/src/common/riscv_internal.h
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Expand Up @@ -160,67 +160,6 @@ static inline void putreg64(uint64_t v, const volatile uintreg_t a)
__asm__ __volatile__("sd %0, 0(%1)" : : "r" (v), "r" (a));
}

#define READ_CSR(reg) \
({ \
uintreg_t __regval; \
__asm__ __volatile__("csrr %0, " __STR(reg) : "=r"(__regval)); \
__regval; \
})

#define READ_AND_SET_CSR(reg, bits) \
({ \
uintreg_t __regval; \
__asm__ __volatile__("csrrs %0, " __STR(reg) ", %1": "=r"(__regval) : "rK"(bits)); \
__regval; \
})

#define WRITE_CSR(reg, val) \
({ \
__asm__ __volatile__("csrw " __STR(reg) ", %0" :: "rK"(val)); \
})

#define SET_CSR(reg, bits) \
({ \
__asm__ __volatile__("csrs " __STR(reg) ", %0" :: "rK"(bits)); \
})

#define CLEAR_CSR(reg, bits) \
({ \
__asm__ __volatile__("csrc " __STR(reg) ", %0" :: "rK"(bits)); \
})

#define SWAP_CSR(reg, val) \
({ \
uintptr_t regval; \
__asm__ __volatile__("csrrw %0, " __STR(reg) ", %1" : "=r"(regval) \
: "rK"(val)); \
regval; \
})

#define WRITE_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
WRITE_CSR(CSR_IREG, val); \
})

#define READ_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
READ_CSR(CSR_IREG, val); \
})

#define SET_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
SET_CSR(CSR_IREG, val); \
})

#define CLEAR_INDIRECT_CSR_REG0(reg, val) \
({ \
WRITE_CSR(CSR_ISELECT, reg); \
CLEAR_CSR(CSR_IREG, val); \
})

#define riscv_append_pmp_region(a, b, s) \
riscv_config_pmp_region(riscv_next_free_pmp_region(), a, b, s)

Expand Down
1 change: 1 addition & 0 deletions boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@
****************************************************************************/

#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>

/****************************************************************************
Expand Down
2 changes: 2 additions & 0 deletions boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@
****************************************************************************/

#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>

/****************************************************************************
* Pre-processor Definitions
Expand Down
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