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@riscv-non-isa RISC-V Non-ISA Specifications

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    34 repositories

    • hart-trace-interface

      Public
      This Fast-Track will extract the Hart-Trace Interface chapter from the E-Trace spec and turn it into a standalone spec
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•0•2•3•Updated Aug 7, 2025Aug 7, 2025

    • rvv-intrinsic-doc

      Public
      C
      •
      BSD 3-Clause "New" or "Revised" License
      •102•342•27•15•Updated Aug 7, 2025Aug 7, 2025

    • riscv-toolchain-conventions

      Public
      Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
      Makefile
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      Creative Commons Attribution 4.0 International
      •42•152•11•2•Updated Aug 7, 2025Aug 7, 2025

    • riscv-rpmi

      Public
      RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control
      platformmessagingstandardsinteroperabilityriscvrpmiriscv-rpmi
      Makefile
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      Creative Commons Attribution 4.0 International
      •9•11•2•0•Updated Aug 6, 2025Aug 6, 2025

    • riscv-semihosting

      Public
      Makefile
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      Creative Commons Attribution Share Alike 4.0 International
      •9•31•2•1•Updated Aug 4, 2025Aug 4, 2025

    • riscv-ras-eri

      Public
      The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…
      TeX
      •
      Creative Commons Attribution 4.0 International
      •6•9•1•1•Updated Aug 4, 2025Aug 4, 2025

    • riscv-trace-spec

      Public
      RISC-V Processor Trace Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •56•191•11•5•Updated Aug 4, 2025Aug 4, 2025

    • riscv-arch-test

      Public
      Assembly
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      Apache License 2.0
      •232•580•64•49•Updated Aug 1, 2025Aug 1, 2025

    • riscv-iommu

      Public
      RISC-V IOMMU Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •26•126•0•3•Updated Jul 31, 2025Jul 31, 2025

    • riscv-acpi-rimt

      Public
      RISC-V ACPI I/O Mapping Table Specification
      Makefile
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      Creative Commons Attribution 4.0 International
      •3•5•1•1•Updated Jul 31, 2025Jul 31, 2025

    • riscv-acpi-ffh

      Public
      The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•4•2•2•Updated Jul 31, 2025Jul 31, 2025

    • riscv-asm-manual

      Public
      RISC-V Assembly Programmer's Manual
      Makefile
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      Creative Commons Attribution 4.0 International
      •248•1.5k•10•8•Updated Jul 31, 2025Jul 31, 2025

    • riscv-cbqri

      Public
      This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.
      Makefile
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      Creative Commons Attribution 4.0 International
      •8•6•0•0•Updated Jul 31, 2025Jul 31, 2025

    • riscv-elf-psabi-doc

      Public
      A RISC-V ELF psABI Document
      Python
      •
      Creative Commons Attribution 4.0 International
      •174•793•63•26•Updated Jul 31, 2025Jul 31, 2025

    • e-trace-encap

      Public
      E-Trace Encapsulation Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•5•1•1•Updated Jul 30, 2025Jul 30, 2025

    • riscv-server-platform

      Public
      The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.
      platformserverosstandardsinteroperabilityuefihypervisorsacpirisc-vbrs-i
      TeX
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      Creative Commons Attribution 4.0 International
      •12•18•4•0•Updated Jul 29, 2025Jul 29, 2025

    • riscv-c-api-doc

      Public
      Documentation of the RISC-V C API
      Makefile
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      Creative Commons Attribution 4.0 International
      •47•77•17•3•Updated Jul 25, 2025Jul 25, 2025

    • riscv-sbi-doc

      Public
      Documentation for the RISC-V Supervisor Binary Interface
      Makefile
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      Creative Commons Attribution 4.0 International
      •95•420•13•2•Updated Jul 24, 2025Jul 24, 2025

    • iopmp-spec

      Public
      This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
      C
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      Creative Commons Attribution 4.0 International
      •8•30•1•1•Updated Jul 24, 2025Jul 24, 2025

    • riscv-security-model

      Public
      RISC-V Security Model
      Makefile
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      Creative Commons Attribution 4.0 International
      •17•30•0•1•Updated Jul 24, 2025Jul 24, 2025

    • riscv-external-debug-security

      Public
      The RISC-V External Debug Security Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•19•0•0•Updated Jul 24, 2025Jul 24, 2025

    • riscv-brs

      Public
      The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.
      platformfirmwarestandardsinteroperabilityuefidevicetreeacpismbiosrisc-vbrs-i
      TeX
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      Creative Commons Attribution 4.0 International
      •20•52•15•1•Updated Jul 24, 2025Jul 24, 2025

    • server-soc

      Public
      The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
      TeX
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      Creative Commons Attribution 4.0 International
      •11•24•1•0•Updated Jul 24, 2025Jul 24, 2025

    • riscv-rqsc

      Public
      Specification Documentation Repository for the RQSC RISC-V Quality of Services Controllers Table definition
      Makefile
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      Creative Commons Attribution 4.0 International
      •1•0•0•1•Updated Jul 1, 2025Jul 1, 2025

    • riscv-ap-tee

      Public
      This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
      securityvirtualizationteetsmconfidential-computingconfidential-vmh-extensionsmmttsupervisor-domains
      Makefile
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      Creative Commons Attribution 4.0 International
      •23•58•21•0•Updated May 13, 2025May 13, 2025

    • server-soc-ts

      Public
      Test suite for Server SoC
      C
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      Apache License 2.0
      •7•4•2•2•Updated Mar 29, 2025Mar 29, 2025

    • tg-nexus-trace

      Public
      RISC-V Nexus Trace TG documentation and reference code
      nexustracerisc-v
      C
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      Creative Commons Attribution 4.0 International
      •37•51•9•2•Updated Jan 3, 2025Jan 3, 2025

    • riscv-ap-tee-io

      Public
      This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.
      tee-io
      Makefile
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      Creative Commons Attribution 4.0 International
      •5•11•8•0•Updated Dec 4, 2024Dec 4, 2024

    • riscv-arch-test-reports

      Public
      HTML
      •6•11•0•0•Updated Dec 2, 2024Dec 2, 2024

    • riscv-device-tree-doc

      Public
      RISC-V Specific Device Tree Documentation
      Python
      •3•42•1•1•Updated Jul 9, 2024Jul 9, 2024