Merge pull request #433 from os-fpga/task/EDA-3187/add_setup_lec_sim

updated the script and added simulation

RTL_testcases/titan_benchmarks/cic_integrator/raptor_run.sh

@@ -10,8 +10,8 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=false 
-post_route_sim=false 
+post_synth_sim=true 
+post_route_sim=true 
 bitstream_sim=false
 
 #raptor options
@@ -182,8 +182,11 @@ parse_cga exit 1; }
     [ -z "$ip_name" ] && echo "" || echo "add_design_file ./rapidsilicon/ip/$ip_name/v1_0/$design/src/$design.v">>raptor_tcl.tcl
 
     [ -z "$ip_name" ] && echo "add_include_path ./rtl">>raptor_tcl.tcl || echo "" 
-    [ -z "$ip_name" ] && echo "add_library_path ./rtl">>raptor_tcl.tcl || echo "" 
-    [ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo "" 
+    # [ -z "$ip_name" ] && echo "add_library_path ./rtl">>raptor_tcl.tcl || echo "" 
+    # [ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo "" 
+    [ -z "$ip_name" ] && echo "add_design_file ./rtl/cic_package.sv">>raptor_tcl.tcl || echo "" 
+    [ -z "$ip_name" ] && echo "add_design_file ./rtl/comb.sv">>raptor_tcl.tcl || echo "" 
+    [ -z "$ip_name" ] && echo "add_design_file ./rtl/integrator.sv">>raptor_tcl.tcl || echo "" 
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/$design.sv">>raptor_tcl.tcl || echo "" 
     ##vary design to design
 
@@ -193,7 +196,7 @@ parse_cga exit 1; }
     [ -z "$add_constraint_file" ] && echo "" || echo "add_constraint_file $add_constraint_file">>raptor_tcl.tcl 
 
     if [ "$post_synth_sim" == true ] || [ "$post_route_sim" == true ] || [ "$bitstream_sim" == true ]; then
-        echo "add_simulation_file ./sim/co_sim_tb/co_sim_$design.v ./rtl/$design.v">>raptor_tcl.tcl 
+        echo "add_simulation_file ./sim/co_sim_tb/co_sim_$design.v rtl/comb.sv rtl/integrator.sv rtl/$design.sv">>raptor_tcl.tcl 
         echo "set_top_testbench co_sim_$design">>raptor_tcl.tcl 
     else
         echo ""
@@ -258,6 +261,10 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    # echo "clear_simulation_files">>raptor_tcl.tcl 
+    # echo "setup_lec_sim">>raptor_tcl.tcl  
+    # [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    # [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/titan_benchmarks/cic_integrator/sim/co_sim_tb/co_sim_cic_i.v

@@ -0,0 +1,74 @@
+`timescale 1ns/1ps
+module co_sim_cic_i;
+// Clock signals
+    reg			clk;
+// Reset signals
+    reg			reset_n;
+
+    wire 		[13:0] 		data_out	,	data_out_netlist;
+    reg 		[7:0] 		data_in;
+    reg 		in_dv;
+	integer		mismatch	=	0;
+
+cic_i	golden (.*);
+
+`ifdef PNR_SIM
+	cic_i_post_route route_net (.*, .data_out(data_out_netlist) );
+`else
+	cic_i_post_synth synth_net (.*, .data_out(data_out_netlist) );
+`endif
+
+// clock initialization for clk
+initial begin
+	clk = 1'b0;
+	forever #5.0 clk = ~clk;
+end
+//Reset Stimulus generation
+initial begin
+	$display ("***Reset Test is applied***");
+	reset_n <= 0;
+	{data_in, in_dv } <= 'd0;
+	repeat (2) @(negedge clk);
+	reset_n <= 1;
+	@(negedge clk);
+	compare();
+	$display ("***Reset Test is ended***");
+	//Random stimulus generation
+	repeat(100) @ (negedge clk) begin
+		data_in              <= $urandom();
+		in_dv                <= 1;
+		compare();
+end
+
+	// ----------- Corner Case stimulus generation -----------
+	repeat (2) @(negedge clk);
+	data_in                <= 8'd255;
+	in_dv                  <= 1'd1;
+	compare();
+
+	if(mismatch == 0)
+		$display("**** All Comparison Matched *** \n		Simulation Passed\n");
+	else
+		begin
+		$display("%0d comparison(s) mismatched\nERROR: SIM: Simulation Failed", mismatch);
+		$fatal(1);
+		end
+	repeat(20) @(posedge clk);
+	$finish;
+end
+
+task compare();
+	if ( data_out !== data_out_netlist ) begin
+		$display("Data Mismatch: Actual output: %0d, Netlist Output %0d, Time: %0t ", data_out, data_out_netlist,  $time);
+		mismatch = mismatch+1;
+	end
+	else
+		$display("Data Matched: Actual output: %0d, Netlist Output %0d, Time: %0t ", data_out, data_out_netlist,  $time);
+endtask
+
+initial begin
+	$dumpfile("tb.vcd");
+	$dumpvars;
+end
+
+endmodule