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Merge pull request #439 from os-fpga/task/EDA-3187/add_setup_lec_sim
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EDA-3187 add setup lec sim for 2 designs
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NadeemYaseen authored Nov 4, 2024
2 parents da36b16 + 227f937 commit eb478f2
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Showing 4 changed files with 9 additions and 3 deletions.
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Expand Up @@ -260,6 +260,9 @@ parse_cga exit 1; }
else
echo ""
fi
echo "setup_lec_sim">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
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Expand Up @@ -259,6 +259,9 @@ parse_cga exit 1; }
else
echo ""
fi
echo "setup_lec_sim">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
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Expand Up @@ -24,7 +24,7 @@ module dmx_dpram #(
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
output reg [width-1:0] dout,

input [depth-1:0] a2,
input we2,
Expand All @@ -37,7 +37,7 @@ reg [width-1:0] ram[0:(1 << depth)-1];
always @(posedge clk) begin
if(we)
ram[a] <= di;
do <= ram[a];
dout <= ram[a];
if(we2)
ram[a2] <= di2;
do2 <= ram[a2];
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Expand Up @@ -45,7 +45,7 @@ dmx_dpram channels(
.a(csr_a[8:0]),
.we(csr_channels_we),
.di(csr_di[7:0]),
.do(csr_do_channels[7:0]),
.dout(csr_do_channels[7:0]),

.a2(channel_a),
.we2(1'b0),
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