feat(tapa): update scripts

rapidstream-org · Sep 9, 2024 · 55eb067 · 55eb067
1 parent bb7a9db
commit 55eb067
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Showing 6 changed files with 97 additions and 64 deletions.
diff --git a/benchmarks/tapa_flow/orcDecoder/Makefile b/benchmarks/tapa_flow/orcDecoder/Makefile
@@ -1,25 +1,33 @@
 # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
 # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 
-ROOT_DIR  := $(shell git rev-parse --show-toplevel)
-GRP_UTIL  := $(ROOT_DIR)/common/util/get_group.py
-TEMP_DIR  := $(CURDIR)/build
-RS_TARGET := $(CURDIR)/$(TEMP_DIR)/dse/candidate_3/exported/impl/vitis_run_hw
-TAPA_XO   := $(CURDIR)/design/generated/data_decoding.xo
-PLATFORM  := xilinx_u280_gen3x16_xdma_1_202211_1
-PART      := xcu280-fsvh2892-2L-e
-RUN_FILE  := $(CURDIR)/run.py
+ROOT_DIR         := $(shell git rev-parse --show-toplevel)
+KERNEL_NAME      := data_decoding
+PLATFORM         := xilinx_u280_gen3x16_xdma_1_202211_1
+GRP_UTIL         := $(ROOT_DIR)/common/util/get_group.py
+RS_SCRIPT        := run.py
+TEMP_DIR         := $(CURDIR)/build/$(notdir $(RS_SCRIPT))
+RS_TARGET        := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
+TAPA_XO          := $(CURDIR)/design/generated/data_decoding.xo
+PART             := xcu280-fsvh2892-2L-e
+BUILD_LOG        := $(TEMP_DIR)/build.json
+SUCCESS          := "Build Successful"
+TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
+SLACK_GETTER     := $(ROOT_DIR)/common/util/get_slack.py
 
 all: $(RS_TARGET)
+	$(RSXX)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
+	@echo $(SUCCESS)
 
 $(RS_TARGET):$(TAPA_XO)
-	rapidstream $(RUN_FILE)
+	$(RSXX) $(RS_SCRIPT)
 
 show_groups:
 	rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \
 	-o $(TEMP_DIR)/module_types.csv
 
 
+
 clean:
 	rm -rf $(TEMP_DIR) *.log
 	rm -rf .Xil .run

diff --git a/benchmarks/tapa_flow/orcDecoder/run.py b/benchmarks/tapa_flow/orcDecoder/run.py
@@ -34,7 +34,7 @@
 print("Reducing DSP of (1, 1) to make it less congested")
 factory.reduce_slot_area(1, 1, dsp=100)
 
-rs = RapidStreamTAPA(f"{CURR_DIR}/build")
+rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}")
 
 rs.set_virtual_device(factory.generate_virtual_device())
 rs.add_xo_file(XO_PATH)

diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/Makefile b/benchmarks/tapa_flow/stencil_sasa/high_congestion/Makefile
@@ -1,20 +1,26 @@
 # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
 # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 
-ROOT_DIR  := $(shell git rev-parse --show-toplevel)
-GRP_UTIL  := $(ROOT_DIR)/common/util/get_group.py
-TEMP_DIR  := $(CURDIR)/build
-RS_TARGET := $(CURDIR)/$(TEMP_DIR)/dse/candidate_0/exported/impl/vitis_run_hw
-TAPA_XO   := $(CURDIR)/design/generated/unikernel.xo
-PLATFORM  := xilinx_u280_gen3x16_xdma_1_202211_1
-PART      := xcu280-fsvh2892-2L-e
-RUN_FILE  := $(CURDIR)/run.py
+ROOT_DIR         := $(shell git rev-parse --show-toplevel)
+KERNEL_NAME      := unikernel
+PLATFORM         := xilinx_u280_gen3x16_xdma_1_202211_1
+GRP_UTIL         := $(ROOT_DIR)/common/util/get_group.py
+RS_SCRIPT        := run.py
+TEMP_DIR         := $(CURDIR)/build/$(notdir $(RS_SCRIPT))
+RS_TARGET        := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
+TAPA_XO          := $(CURDIR)/design/generated/unikernel.xo
+PART             := xcu280-fsvh2892-2L-e
+BUILD_LOG        := $(TEMP_DIR)/build.json
+SUCCESS          := "Build Successful"
+TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
+SLACK_GETTER     := $(ROOT_DIR)/common/util/get_slack.py
 
 all: $(RS_TARGET)
+	$(RSXX)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
+	@echo $(SUCCESS)
 
 $(RS_TARGET):$(TAPA_XO)
-	rapidstream $(RUN_FILE)
-
+	$(RSXX) $(RS_SCRIPT)
 
 show_groups:
 	rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \

diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/run.py b/benchmarks/tapa_flow/stencil_sasa/high_congestion/run.py
@@ -34,7 +34,7 @@
 print("Reducing DSP of (1, 1) to make it less congested")
 factory.reduce_slot_area(1, 1, dsp=100)
 
-rs = RapidStreamTAPA(f"{CURR_DIR}/build")
+rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}")
 
 rs.set_virtual_device(factory.generate_virtual_device())
 rs.add_xo_file(XO_PATH)

diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/Makefile b/benchmarks/tapa_flow/stencil_sasa/low_congestion/Makefile
@@ -1,20 +1,26 @@
 # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
 # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 
-ROOT_DIR  := $(shell git rev-parse --show-toplevel)
-GRP_UTIL  := $(ROOT_DIR)/common/util/get_group.py
-TEMP_DIR  := $(CURDIR)/build
-RS_TARGET := $(CURDIR)/$(TEMP_DIR)/dse/candidate_0/exported/impl/vitis_run_hw
-TAPA_XO   := $(CURDIR)/design/generated/unikernel.xo
-PLATFORM  := xilinx_u280_gen3x16_xdma_1_202211_1
-PART      := xcu280-fsvh2892-2L-e
-RUN_FILE  := $(CURDIR)/run.py
+ROOT_DIR         := $(shell git rev-parse --show-toplevel)
+KERNEL_NAME      := unikernel
+PLATFORM         := xilinx_u280_gen3x16_xdma_1_202211_1
+GRP_UTIL         := $(ROOT_DIR)/common/util/get_group.py
+RS_SCRIPT        := run.py
+TEMP_DIR         := $(CURDIR)/build/$(notdir $(RS_SCRIPT))
+RS_TARGET        := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
+TAPA_XO          := $(CURDIR)/design/generated/unikernel.xo
+PART             := xcu280-fsvh2892-2L-e
+BUILD_LOG        := $(TEMP_DIR)/build.json
+SUCCESS          := "Build Successful"
+TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
+SLACK_GETTER     := $(ROOT_DIR)/common/util/get_slack.py
 
 all: $(RS_TARGET)
+	$(RSXX)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
+	@echo $(SUCCESS)
 
 $(RS_TARGET):$(TAPA_XO)
-	rapidstream $(RUN_FILE)
-
+	$(RSXX) $(RS_SCRIPT)
 
 show_groups:
 	rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \

diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/run.py b/benchmarks/tapa_flow/stencil_sasa/low_congestion/run.py
@@ -34,7 +34,7 @@
 print("Reducing DSP of (1, 1) to make it less congested")
 factory.reduce_slot_area(1, 1, dsp=100)
 
-rs = RapidStreamTAPA(f"{CURR_DIR}/build")
+rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}")
 
 rs.set_virtual_device(factory.generate_virtual_device())
 rs.add_xo_file(XO_PATH)
@@ -54,60 +54,73 @@
 # sp=unikernel.out_0:HBM[1]
 # sp=unikernel.in_1:HBM[2]
 # sp=unikernel.out_1:HBM[3]
-# sp=unikernel.in_3:HBM[4]
-# sp=unikernel.out_3:HBM[5]
-# sp=unikernel.in_6:HBM[6]
-# sp=unikernel.out_6:HBM[7]
-# sp=unikernel.in_9:HBM[8]
-# sp=unikernel.out_9:HBM[9]
-# sp=unikernel.in_11:HBM[10]
-# sp=unikernel.out_11:HBM[11]
-# sp=unikernel.in_2:HBM[12]
-# sp=unikernel.out_2:HBM[13]
+# sp=unikernel.in_2:HBM[4]
+# sp=unikernel.out_2:HBM[5]
+# sp=unikernel.in_3:HBM[6]
+# sp=unikernel.out_3:HBM[7]
+# sp=unikernel.in_4:HBM[8]
+# sp=unikernel.out_4:HBM[9]
+# sp=unikernel.in_5:HBM[10]
+# sp=unikernel.out_5:HBM[11]
+# sp=unikernel.in_6:HBM[12]
+# sp=unikernel.out_6:HBM[13]
+# sp=unikernel.in_7:HBM[14]
+# sp=unikernel.out_7:HBM[15]
+
 
 left_args = [
     "in_0",
     "out_0",
     "in_1",
     "out_1",
+    "in_2",
+    "out_2",
     "in_3",
     "out_3",
+    "in_4",
+    "out_4",
+    "in_5",
+    "out_5",
     "in_6",
     "out_6",
-    "in_9",
-    "out_9",
-    "in_11",
-    "out_11",
-    "in_2",
-    "out_2",
+    "in_7",
+    "out_7",
 ]
 
 for arg in left_args:
     rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot)
 
 # The config file binds the following argument to HBM 16 - 31
-# sp=unikernel.in_4:HBM[18]
-# sp=unikernel.out_4:HBM[19]
-# sp=unikernel.in_5:HBM[20]
-# sp=unikernel.out_5:HBM[21]
-# sp=unikernel.in_7:HBM[22]
-# sp=unikernel.out_7:HBM[23]
-# sp=unikernel.in_8:HBM[24]
-# sp=unikernel.out_8:HBM[25]
-# sp=unikernel.in_10:HBM[26]
-# sp=unikernel.out_10:HBM[27]
+# sp=unikernel.in_8:HBM[17]
+# sp=unikernel.out_8:HBM[18]
+# sp=unikernel.in_9:HBM[19]
+# sp=unikernel.out_9:HBM[20]
+# sp=unikernel.in_10:HBM[21]
+# sp=unikernel.out_10:HBM[22]
+# sp=unikernel.in_11:HBM[23]
+# sp=unikernel.out_11:HBM[24]
+# sp=unikernel.in_12:HBM[25]
+# sp=unikernel.out_12:HBM[26]
+# sp=unikernel.in_13:HBM[27]
+# sp=unikernel.out_13:HBM[28]
+# sp=unikernel.in_14:HBM[29]
+# sp=unikernel.out_14:HBM[30]
 
 right_args = [
-    "in_4",
-    "out_4",
-    "in_5",
-    "out_5",
-    "in_7",
-    "out_7",
     "in_8",
     "out_8",
+    "in_9",
+    "out_9",
     "in_10",
     "out_10",
+    "in_11",
+    "out_11",
+    "in_12",
+    "out_12",
+    "in_13",
+    "out_13",
+    "in_14",
+    "out_14",
 ]
 
 for arg in right_args: