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Sifive rvv intrinsic xsfvcp #7

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@yulong18 yulong18 commented Dec 6, 2024

This pr tries add the intrinsics support for Xsfvcp extension.

@yulong18 yulong18 force-pushed the sifive-rvv-intrinsic-xsfvcp branch from e242c05 to 865eb47 Compare December 9, 2024 02:09
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yulong18 commented Dec 9, 2024

Hi, @kito-cheng :
Please help to review the code, thanks.
^_^

@yulong18 yulong18 force-pushed the sifive-rvv-intrinsic-xsfvcp branch from 865eb47 to c944e05 Compare December 9, 2024 03:06
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  • I would like to use O[us][0-9][0-9] as a generic immediate operand modifier, so that it can used in other places as well, do you have intestest to post a proposal to riscv-c-api-doc like [RISCV] Inline Assembly: RVC constraint and N modifier llvm/llvm-project#112561

  • could you add vsetvli check in the test case?

  • We don't need X2 here, could you check how wadd.vv and wadd.vx implement? use double_trunc_vector should be work in this case once you adjust the base SEW/LMUL right.

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Could you reduce the test files? just one test for each instruction is fine, you don't need put all test into gcc source tree.

e.g. only pick test_sf_vc_v_xvw_u8mf4 and test_sf_vc_v_xvw_se_u16m4 for sf.vc.v.xvw

Comment on lines 186 to 204
;; SF_VCP
(define_insn "@sf_vc_x<mode>"
[(set (match_operand:VFULLI 0 "register_operand" "=vd")
(if_then_else:VFULLI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " Wc1")
(match_operand 7 "vector_length_operand" " rK")
(match_operand 8 "const_int_operand" " i")
(match_operand 9 "const_int_operand" " i")
(match_operand 10 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VFULLI
[(match_operand:SI 3 "const_int_operand" "B")
(match_operand:SI 4 "const_int_operand" "K")
(match_operand:SI 5 "const_int_operand" "K")
(match_operand:<VEL> 6 "register_operand" "r")] UNSPEC_SF_CV)
(match_operand:VFULLI 2 "vector_merge_operand" "vu")))]
"TARGET_VECTOR && TARGET_XSFVCP"
"sf.vc.x\t %3, %4, %5, %6"
[(set_attr "type" "sf_vc_se")
(set_attr "mode" "<MODE>")])
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For those instruction without output, you don't really need a dummy output operand there, you just need some thing like

gcc/config/riscv/sifive-vector.md Outdated Show resolved Hide resolved
@yulong18 yulong18 force-pushed the sifive-rvv-intrinsic-xsfvcp branch 2 times, most recently from a4b780d to 2c96c6a Compare December 18, 2024 08:52
pz9115 and others added 4 commits December 19, 2024 10:57
gcc/ChangeLog:

	* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
	(main):
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS):
	(vint8mf8_t):
	(vint8mf4_t):
	(vint8mf2_t):
	(vint8m1_t):
	(vint8m2_t):
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS):
	(rvv_arg_type_info::get_xfqf_float_type):
	* config/riscv/riscv-vector-builtins.def (xfqf_vector):
	(xfqf_float):
	* config/riscv/riscv-vector-builtins.h (struct rvv_arg_type_info):
	* config/riscv/sifive-vector.md:
	* config/riscv/vector-iterators.md:
@yulong18 yulong18 force-pushed the sifive-rvv-intrinsic-xsfvcp branch from 2c96c6a to bcc379f Compare December 19, 2024 03:59
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4 participants