- About
- Interface Description
- Performance and Resource Utilization
- Testing
- Status Information
- Licence
This repository contains an integer divider module. And old and slower divider design can be found in directory obsolete, but not suggested to be used.
Following parameters can be used to modify the size of operation and the output flags.
Parameter | Possible Values | Description |
---|---|---|
WIDTH |
integer | Operation size |
CACHING |
bool | Enable result caching |
INIT_VLD |
bool | In reset state set valid flag |
CACHING
: When enabled, if same operands as previous calculation given, directly set valid flag. This requires additional logic and registers.
Ports of the all modules/IPs named in same manner.
Port | Type | Width | Description | Notes |
---|---|---|---|---|
clk |
I | 1 | System Clock | |
rst |
I | 1 | System Reset | |
start |
I | 1 | Start Calculation | |
dividend |
I | WIDTH |
Dividend Operand | |
divisor |
I | WIDTH |
Divisor Operand | |
quotient |
O | WIDTH |
Quotient Result | |
remainder |
O | WIDTH |
Remainder Result | |
zeroErr |
O | 1 | Divide by Zero Error | |
valid |
O | 1 | Outputs are Valid |
I: Input O: Output
All values in this section are for Xilinx Artix-7 (XC7A100TCSG324-1) FPGA with caching enabled and init valid disabled.
- Utilization after synthesis: 125 LUT as Logic and 108 Register as Flip Flop
- Maximum tested clock frequency (with input output registers): 200 MHz
- Utilization after synthesis: 237 LUT as Logic and 205 Register as Flip Flop
- Maximum tested clock frequency (with input output registers): 150 MHz
Files related to testing can be found in Testing directory. Test block diagram contains a VIO and a ILA connected to divider module. Each connection contains a pipeline register.
- Simulation: 27 July 2023 with Vivado Simulator 2021.1.1.
- Test: 27 July 2023 with Digilent Arty A7
CERN Open Hardware Licence Version 2 - Weakly Reciprocal