FPGA interface and driver for an OV7670 camera sensor.

This is a collection of some examples designed in the Vivado Design Suite.

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

A 2x2 mesh NoC compatible with AXI streaming interface

A one-position buffer compatible with AXI Stream interface

A demonstrator of Hermes network-on-chip communicating with the ARM processor

Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface

Formal verification of an ALU

A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source

Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.

Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

AXI stream protocol checking design

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Notes after working with Zynq platform using vivado and petalinux

ASIC for executing vectorized gradient descent on linear regression problems.

vivado design to test the skidbuffer IP

Synchronous and Asynchronous FIFO with AXI interface

An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals

A one-position buffer compatible with AXI Stream interface

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device