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bcd-to-7-segment

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Vedant-02 / Verilog-HDL-Lab-Experiments

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Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

verilog hacktoberfest barrel-shifter full-adder carry-look-ahead-adder 4-bit-comparator carry-select-adder adder-subtractor bcd-adder binary-multiplier binary-to-gray hacktoberfest2022 32-bit-alu priority-encoder 4-bit-parallel-adder 4-bit-combinational-adder bcd-to-7-segment 32-bit-fast-adder carry-skip-adder bcd-subtractor
  • Updated Oct 23, 2022
  • Verilog
8051-7Segment

gmostofabd / 8051-7Segment

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📦 This repository demonstrates how to interface a single-digit Seven-Segment Display (SSD) with the 8051 microcontroller using assembly language. A common cathode SSD is utilized in this project, with all necessary files provided, including assembly code, Proteus simulation files, HEX files, and photos from testing. Later we included 2 digits exam

hex microcontroller programming simulation assembly decoder file schematic ssd proteus 8051 seven-segments-display common-cathode bcd-to-7-segment circuity common-anode-display
  • Updated Sep 23, 2024
  • HTML

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