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Vedant-02 / Verilog-HDL-Lab-Experiments

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Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

verilog hacktoberfest barrel-shifter full-adder carry-look-ahead-adder 4-bit-comparator carry-select-adder adder-subtractor bcd-adder binary-multiplier binary-to-gray hacktoberfest2022 32-bit-alu priority-encoder 4-bit-parallel-adder 4-bit-combinational-adder bcd-to-7-segment 32-bit-fast-adder carry-skip-adder bcd-subtractor
  • Updated Oct 23, 2022
  • Verilog

ammarmalik17 / Verilog_Adders

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This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
  • Updated Aug 24, 2024
  • Verilog

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