Python Control System : Create control loops and let the AI set the PID parameters
-
Updated
Jan 30, 2025 - Python
#
control-unit
Here are 23 public repositories matching this topic...
Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.
solutions hardware memory processor computer switching logic-programming logic-gates logic-circuit digital-design binary-logic control-unit arithmetic-logic-unit nandgame fundamentals-of-computing arithmetic-circuits nand-game thenandgame-solutions logic-unit random-access-memory
-
Updated
Nov 4, 2023
Inverted Pendulum in python with pybox2d. Fuzzy and PID simulation included.
-
Updated
Jan 24, 2021 - Python
This is an implementation of a simple CPU in Logisim and Verilog.
cpu instructions assembler alu logisim modelsim control-unit cpu-design cpu-simulation register-file data-memory address-memory
-
Updated
Jan 11, 2019 - Verilog
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor
-
Updated
Jan 24, 2021 - Verilog
🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.
python state-machine memory processor instrumentation verilog buffers computer-architecture registers program-counter control-unit pipline pipline-operators cufe-2024 execution-unit pipelined-processor
-
Updated
Oct 16, 2023 - Verilog
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
instructions datapath alu logisim program-counter control-unit register-file data-memory instruction-memory
-
Updated
Jun 23, 2021
Implementation of a microprogrammed control unit for didactic purpose
-
Updated
Dec 5, 2017 - C
An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.
-
Updated
Feb 8, 2021 - VHDL
simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.
-
Updated
Jun 5, 2023 - Verilog
fpga memory processor verilog vivado datapath alu verilog-hdl risc-v digital-design control-unit fpga-programming
-
Updated
Mar 12, 2023 - Verilog
Software for 3-axis machine control. It uses a Raspberry Pi with motor controllers and additional electronics. Features: visualization, GPIO emulation, touchscreen capability, and Cython optimization. Tested on Windows(visu) and Raspberry Pi OS. Under development with Pyside2 and OpenGl.
visualization python raspberry-pi opengl gpio raspberrypi pyqt5 python3 gui-application pyside2 circuit py 3d wavefront-obj motor-driver diploma-project qt-designer control-unit raspberry-pi-4
-
Updated
Jul 1, 2023 - Python
My Solutions to Computer Architecture Course Practical Assignments
cache processor vhdl computer-architecture alu fifo fifo-queue multiplier control-unit direct-mapped-cache
-
Updated
Sep 2, 2024 - VHDL
-
Updated
Aug 31, 2018
Using Python creating simulation of Control unit
-
Updated
Apr 15, 2019 - Python
The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.
-
Updated
Apr 9, 2024 - HTML
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
simulation user-interface computer-architecture instruction-set-architecture code-execution mips-simulator 16-bit-cpu control-unit processor-design cpu-design logic-circuits gui-dashboard custom-processor
-
Updated
Aug 6, 2024 - JavaScript
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
-
Updated
Jan 29, 2023 - Verilog
This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.
-
Updated
Oct 11, 2024 - JavaScript
16 bit processor designed in logisim
-
Updated
Jun 26, 2021 - Verilog
Improve this page
Add a description, image, and links to the control-unit topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the control-unit topic, visit your repo's landing page and select "manage topics."