"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

All my projects, homework, hand writings, course slides and anything I have learned and done during my studies at IUT😊. feel free to give it a ⭐=)

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

Final Project for Digital Systems Design Course, Fall 2020

My activity in digital systems

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

This GitHub repository Consists of materials, code samples, documentation, and valuable resources related to the Information Technology (IT) Department at the National Institute of Technology Karnataka (NITK). 📚 Resource Library 💻 Code Samples 🗂️ Project Repositories

Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]

3-stage RISC-V Pipelined Processor with interrupt CSR support

Repositorio con las 12 prácticas en VHDL para el curso impartido por la profesora Nayeli Vega, tomada en la ESCOM, IPN.

Term project and lab assignments for CS303 - Logic and Digital System course in Sabancı University, Fall 2021-2022.

Digital Systems Design - Spring 2023 - Sharif University of Technology

Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.

Lab projects using Verilog HDL

Implementation of a low-pass FIR filter in Verilog HDL.

Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

Digital System Design Course (1st year, 2nd Semester)

This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.