Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
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Updated
Dec 28, 2024 - Verilog
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] | SE Semester III | Computer Engineering
Implementation of a low-pass FIR filter in Verilog HDL.
Digital Systems Design, Sharif University of Technology Fall 2022, Instructor: Dr. Amin Foshati
Design and Implementation of an ESP32 Based Morse Communication System
Digital Systems Design Lab, Sharif University of Technology Fall 2022
This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc..
Cache Controller Project for COE758 Digital Systems Engineering.
A Tic Tac Toe game made completely using digital logic. A semester project for the course Digital System Design
👾 My studies with Verilog and notions of digital systems.
My Verilog Codes for Digital Systems Design Course
COE758 - This course covers advanced computing systems with emphasis on system architecture, memory hierarchy (Cache, Virtual memory), processor-peripheral interfacing, and bus organization. Laboratory projects include Cache Controller and VGA display design using FPGA. This course is taken at TMU, formally known as Ryerson.
Academic Materials – Semester 3 | Part of the Cosmos Vault multi-semester collection.
Repository focused on giving a complete introductory course to digital systems, applied to robotics and automation.
Seven instructions digital processor for general purpose.
DSDS (Digital system design and synthesis) Lab and class programs of 2021 - 25 batch.
Digital systems class at uni
A multi phase implementation of a simple CPU (Adding Machine) in Verilog
My interests and some collaborations
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