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full-adder

Here are 44 public repositories matching this topic...

nxbyte / Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder

Updated Oct 2, 2019
Verilog

Elidevin / nandgame.com-solutions

Solutions for NandGame.com

register alu xor full-adder nandgame data-flip-flop

Updated Oct 5, 2023

luckykadam / adder

Binary Adder using RNN in Keras

tensorflow keras recurrent-neural-networks full-adder binary-addition

Updated Jul 21, 2020
Jupyter Notebook

bespoyasov / binary-full-adder-in-the-game-of-life

Binary adder implementation in the Game of Life written in JavaScript using canvas.

tutorial game-of-life digital-logic half-adder full-adder

Updated May 18, 2022
JavaScript

Stavros / Multiplier4bit

A 4bit Multiplier in VHDL

fpga vhdl half-adder vhdl-code vhdl-examples full-adder

Updated Feb 3, 2020
VHDL

Keerthiraj-Nagaraj / IBM-quantum-challenge-2020

My solutions to 5 exercises of IBM quantum challenge 2020. Topics include quantum full-adder circuit implementation, circuit optimization and solving various puzzles using Grover's search algorithm.

quantum-computing quantum-gates asteroids-game ibm-quantum-experience qiskit grovers-algorithm full-adder lights-out-game ibm-quantum-challenge quantum-gate-optimization

Updated Dec 7, 2020
Jupyter Notebook

Zannatul-Naim / Digital-System-Design

Digital System Design Lab Codes using Verilog

verilog adder half-adder d-flipflop full-adder flipflop ripple-carry-adder jk-flipflop t-flipflop

Updated Nov 27, 2022
Verilog

Vedant-02 / Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Updated Oct 23, 2022
Verilog

MohammadNiknam17 / Signed-4BIT-Binary-Multiplier_VHDL-FPGA

These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.

fpga binary vhdl signed fulladder 4bit multiplier halfadder vhdl-code full-adder baugh-wooley

Updated May 10, 2021
VHDL

vending_machine_processor

MohammadNiknam17 / vending_machine_processor

VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.

fsm fpga processor vhdl mux vendingmachine comparator accumulator vending-machine vhdl-code full-adder

Updated Jul 20, 2021
VHDL

DatDarkAlpaca / dat-emulation-sandbox

A simulation where I can connect virtual logic gates and build virtual CIs.

alu half-adder full-adder logic-gates-simulator op-codes

Updated Dec 26, 2022
C++

utkarshad21 / 4-bit-Full-Adder-using-Verilog-HDL

Verilog code and testbench for 4-bit full adder

verilog adder full-adder verilog-project verilog-code 4-bit-adder

Updated Jul 11, 2024
Verilog

PARSA-MHMDI / design-ALU-with-Xilinx-ISE

This is Amirkabir University Logic Circuit Design final project 2022

cpu register simulation vhdl xilinx alu logic-circuit xilinx-ise full-adder common-base

Updated Aug 5, 2022
C

jhenals / VHDL-Code---Carry-Select-32bit

Progetto di Elettronica Digitale AA 2022-2023

multiplexer vhdl-code vhdl-coursework full-adder vdhl ripple-carry-adder carry-select-adder ripple-carry

Updated Feb 20, 2023

jamestiotio / DigiAlpha

Optimized 32-Bit Full Adder, CEC-SAT Verifier & 2-SAT Solver

algorithm algorithms satisfiability-solver hardware-designs sat-solver adder tarjan-algorithm dpll algorithms-and-data-structures satisfiability adders full-adder satisfiability-problem implication-graph cec-verifier kosaraju-algorithm

Updated Dec 1, 2023
C++

imvickykumar999 / Logical-Redstone-Reloaded

Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/

world ram binary memory clock cycle redstone ticks rom minecraft-resourcepack flip-flop half-adder latch combinational-circuit full-adder sequential-circuit full-subtractor half-subtractor

Updated Aug 20, 2023
Python

joeymaillette04 / VHDL

VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design

vhdl digital-design half-adder combinational-logic binary-logic full-adder 4-bit-combinational-adder

Updated Oct 18, 2023
VHDL

rahul21316 / verilog-adders

All the various adders in Verilog!

half-adder full-adder ripple-carry-adder

Updated May 31, 2021

aliansgp / VHDL_Adders

Different adders code in VHDL and Comparison

vhdl vhd computer-architecture adder computer-architecture-lesson half-adder vhdl-code adders vhdl-examples full-adder ripple-adder look-ahead-adder carry-save-adder

Updated Feb 7, 2023
C

CedricRev / simple-calculator-verilog

An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.

verilog multiplexer multiplier full-adder adder-subtractor

Updated Jan 26, 2024
Verilog

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