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Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Single-cycle RISC CPU with 5-stage pipeline and multiplication & division support based on RV32I, verified & deployed rotating leds on Genesys2.
Updated
Apr 5, 2023
Verilog
The E203 Hbirdv2 RISC-V Core transplanted on Genesys2
Updated
Sep 11, 2022
Verilog
Hbird SDK, with more examples and Genesys2 supported
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Very simple CPU(4 instructions) deployed & verified on FPGA Genesys2.
Updated
Mar 16, 2023
VHDL
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