Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

A ZipCPU SoC for the Nexys Video board supporting video functionality

VeeRwolf (a platform for the VeeR family of RISC-V cores) for Nexys Video Board: https://github.com/chipsalliance/VeeRwolf

A guide on how to write basic FPGA programming in VHDL and its implementation. This targeted the one who has no experience with Vivado.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Sudoku Solver using the Nexys Video board

Slaves for AXI-lite interface

Microblaze demo for Vivado and Vitis 2024.1.