ghdl
Here are 80 public repositories matching this topic...
An abstraction library for interfacing EDA tools
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Feb 13, 2025 - Python
Repurposing existing HDL tools to help writing better code
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Jun 6, 2024 - Python
SPI master and SPI slave for FPGA written in VHDL
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Apr 24, 2021 - VHDL
Simple UART controller for FPGA written in VHDL
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Aug 7, 2021 - VHDL
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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Feb 2, 2025 - VHDL
Trying to verify Verilog/VHDL designs with formal methods and tools
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Mar 7, 2024 - VHDL
cryptography ip-cores in vhdl / verilog
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Feb 20, 2021 - VHDL
✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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Feb 10, 2025 - Python
Library of reusable VHDL components
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Mar 7, 2024 - VHDL
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
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Nov 20, 2024 - VHDL
HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.
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Feb 10, 2025 - Python
Custom 64-bit pipelined RISC processor
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Jul 18, 2024 - VHDL
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