FPGA synthesis tool powered by program synthesis
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Updated
Dec 15, 2025 - Racket
FPGA synthesis tool powered by program synthesis
A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.
Hardware accelerator for Capsule Neural Networks
Verilog to redstone compiler + synthesiser for Minecraft
Code written during 2110363 HW SYN LAB I course, Academic Year 2021, Chulalongkorn University.
Design for 4 bit ALU with essential logical and arithmetic modules.
An 8-bit RISC Microprocessor made for my Embedded Systems course.
Digital Logic Design project at Politecnico di Milano
A nextpnr arch definition for the TuringTumble board game.
Non-dissipative computational engine implementing the Unitary Transduction Invariant (ΔI · Φ = W_rec). Bypasses the Landauer limit via Golden Ratio (Φ) phase-synchronization. Eliminates thermal resonance by re-channeling entropy into recirculative work. Written in Rust.
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