💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.

Algorithm to simulate tomasulo algorithm. The algorithm shows step by step output.

Simulation of the Tomasulo algorithm using python and verilog.Python code has been included to simulate dynamic instruction scheduling.This project was done as the part of Computer Architecture course.

An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.

A Tomasulo & Scoreboarding Visual Simulator

Simulates Tomasulo Algorithms with Reorder Buffer

Python simulator of Tomasulo algorithm

A RISC-V RV32I cpu simulator, featuring tomasulo algorithm and hardware speculation.

Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm

Dynamic scheduling with Tomasulo's algorithm

Simulation of the Tomasulo architecture and algorithm for microprocessors

A MIPS CPU simulator for Tomasulo algorithm (pthread implementation)

🧲 Tomasulo Simulator - A speculative TFSim with a GUI. Implementation, evaluation, and validation of dynamic branch predictors.

Tomasulo simulator.

Tomasulo algorithm, Python Implementation

Simulador do algoritmo de Tomasulo.

A speculative tomasulo simulator with ROB(Reorder Buffer)

Implement tomasulo algorithm

This is a VHDL implementation of the Tomasulo algorithm with Reorder Buffer within the university Lesson of Computer Architecture