Mealy State Machine for Sequence Detection

mealySD11010.v is the verilog code implementation of Sequence Detector for 11010 using mealy machine. This repository contains the Verilog implementation of a Mealy state machine designed to detect the input sequence "11010". The state machine transitions through five states based on the input signal and asserts an output when the sequence is detected. The implementation includes a testbench to verify the functionality of the state machine. The state machine is non-overlapping, meaning it does not detect overlapping occurrences of the sequence. This project is useful for understanding state machine design and sequence detection in digital systems.