Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

dts: Provide Serial-wire / JTAG pin description #180

Merged
merged 3 commits into from
Jan 18, 2024

Conversation

erwango
Copy link
Member

@erwango erwango commented Oct 6, 2023

Provide Serial Wire / JTAG signal description.

Aim is to provide the ability to disable them (set to analog) in case is it possible and power consumption matters.
We don't provide a full extent description (speed, pull-down, ..) as there is no intention to support runtime change
of state from sleep to functional mode.

"-" could be used in signal names in .xml files.
This character is not allowed in dts format so replace it by "_"
before generation.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Copy link
Collaborator

@gautierg-st gautierg-st left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Nothing is added for C0/F0/G0/L0. Is it intentional?

scripts/genpinctrl/stm32-pinctrl-config.yaml Outdated Show resolved Hide resolved
Generate Serial Wire and JTAG port pins definitions.
The particularity of these signals is that they are part of
default SoC boot time configuration (in order to enable debug at boot time
with no SW configuration required).

The reason we need to define them is to enable the ability to set
JTAG port pins in analog mode when they are not needed in order to
save power (set them to analog).

Today, the use case of dynamic configuration from analog back to a
functional SWJ state is not taken into account, hence we're not generating
the complete pin configuration (including possible pull-down or slew-rate
combinations).

Similarly, we're not generating these signals on STM32F1 as default SoC
configuration is analog state. Hence no need to be taken into account
for the required functionality.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
SWJ signals have been generated.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
@erwango erwango merged commit 60c9634 into zephyrproject-rtos:main Jan 18, 2024
4 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants