NXP LPSPI: Fix some regressions #86156
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decsny
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Raymond0225
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Feb 21, 2025
| while ((base->CR & LPSPI_CR_MEN_MASK) != 0U) { | ||
| /* Wait until LPSPI is disabled. Datasheet: | ||
| * After writing 0, MEN (Module Enable) remains set until the LPSPI has | ||
| * completed the current transfer and is idle. | ||
| */ | ||
| } | ||
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| base->CR |= LPSPI_CR_RST_MASK; | ||
| base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; |
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I think you can remove these lines as they have already initialized in LPSPI_MasterInit
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actually, I just realized, they are still in the wrong place, the purpose of this was to fix S32 silicon errata
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@Raymond0225 I updated the PR to do an alternative workaround but I still need to test on S32 hardware, so it will remain on draft still
The LPSPI FIFOs on this platform are 8 words long, not 16. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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No need to reconfigure SPI if already configured with same configuration. This reduces latency of some transfers that re-use the same spi_cfg. Also, a slightly related change is to remove the setting of the CONTC bit in the init. This was a mistake to have because there was no intention to do a continuing command and could cause some problem, or at least cause confusion to readers of the driver code. Signed-off-by: Declan Snyder <declan.snyder@nxp.com> Co-authored-by: Raymond Lei <raymond.lei@nxp.com>
On some of the platforms, the module doesn't get clocked until the SDK Init call, causing the control register (CR) write to fault. The reason for this code in the first place was to avoid S32 chip errata that caused fifos to need internal logic reset. Since we want to avoid reconfiguring, and a module reset would require that, there is one other documented workaround which is to just read the RX fifo register to update the internal hardware pointer. For the TX fifo the fix is to wait for transfer completion which should be done by the point of starting a new one. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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Fixes #86148
Fixes #86145
One patch on this PR is from @Raymond0225