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Revert "refactor: Formatting and syntax fixes"
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This reverts commit 948ade6.
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@ShinyMiraidon
ShinyMiraidon authored Feb 8, 2024
1 parent 948ade6 commit dbc34b8
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Showing 17 changed files with 293 additions and 382 deletions.
12 changes: 5 additions & 7 deletions CMakeLists.txt
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@@ -1,6 +1,6 @@
cmake_minimum_required(VERSION 3.27)
cmake_minimum_required(VERSION 3.24)

if(NOT SKIP_VCPKG AND NOT DEFINED CMAKE_TOOLCHAIN_FILE)
if(NOT DEFINED CMAKE_TOOLCHAIN_FILE)
include(FetchContent)
FetchContent_Declare(
vcpkg
Expand All @@ -16,11 +16,9 @@ if(NOT SKIP_VCPKG AND NOT DEFINED CMAKE_TOOLCHAIN_FILE)
set(VCPKG_ROOT_DIR ${vcpkg_SOURCE_DIR} CACHE PATH "Vcpkg Root Directory")
endif()

if(DEFINED VCPKG_ROOT_DIR)
add_custom_target(UpdateVcpkgBaseline
${VCPKG_ROOT_DIR}/vcpkg x-update-baseline
)
endif()
add_custom_target(UpdateVcpkgBaseline
${VCPKG_ROOT_DIR}/vcpkg x-update-baseline
)

project(nyu-core VERSION 1.0.0)

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47 changes: 29 additions & 18 deletions rtl/Alu.sv
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Expand Up @@ -13,26 +13,37 @@ parameter USLT = 6'h03;


module Alu #(
WordSize = 32
) (
input [WordSize - 1:0] a,
input [WordSize - 1:0] b,
WordSize = 32
)(
input [WordSize - 1:0] a, b,
input [5:0] alu_mode,
output logic [WordSize - 1:0] alu_out
);
always_comb begin
case (alu_mode)
ADD: alu_out = a + b;
SUB: alu_out = a - b;
XOR: alu_out = a ^ b;
OR: alu_out = a | b;
AND: alu_out = a & b;
LLS: alu_out = a << b[4:0];
LRS: alu_out = a >> b[4:0];
ARS: alu_out = $signed(a) >>> b[4:0];
SSLT: alu_out = WordSize'($signed(a) < $signed(b));
USLT: alu_out = WordSize'(a < b);
default: alu_out = 0;

logic[WordSize - 1:0] adder_result;
logic do_sub, carry;

assign do_sub = alu_mode[5] | (alu_mode == SSLT) | (alu_mode == USLT);

assign {carry, adder_result} = {1'b0, a} + {1'b0, ((b^({WordSize{do_sub}})) + {{WordSize - 1{1'b0}}, do_sub})};

always_comb begin
case(alu_mode)
ADD: alu_out = adder_result;
SUB: alu_out = adder_result;
XOR: alu_out = a ^ b;
OR: alu_out = a | b;
AND: alu_out = a & b;
LLS: alu_out = a << b[4:0];
LRS: alu_out = a >> b[4:0];
ARS: alu_out = a >>> b[4:0];
SSLT: alu_out = (a[WordSize - 1] & !(b[WordSize - 1])) ? 1 : (!(a[WordSize - 1]) & b[WordSize - 1]) ? 0 : {{WordSize - 1{1'b0}}, carry^(!b[WordSize - 1])};
USLT: alu_out = {{WordSize - 1{1'b0}}, !carry};
default: alu_out = 0;
endcase
end


end


endmodule
76 changes: 36 additions & 40 deletions rtl/Branch_Addr_Calc.sv
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@@ -1,48 +1,44 @@
//Branch Address Conditions
parameter PC = 0; //Case when branch_addr = pc + imm
parameter RD = 1; //Case when branch_addr = imm + rs1d
parameter PC = 0; //Case when branch_addr = pc + imm
parameter RD = 1; //Case when branch_addr = imm + rs1d

module Branch_Addr_Calc #(
module Branch_Addr_Calc # (
WordSize = 32
) (
input addr_mode,
input branch_taken,
input [WordSize - 1:0] imm,
input [WordSize - 1:0] rs1d,
input [WordSize - 1:0] pc_in,
output logic [WordSize - 1:0] branch_addr,
output logic [WordSize - 1:0] npc
)(
input addr_mode, branch_taken,
input [WordSize - 1:0] imm, rs1d, pc_in,
output logic [WordSize - 1:0] branch_addr, npc
);

always_comb begin
case (addr_mode)
PC:
case (branch_taken)
1'b0: begin
branch_addr = pc_in + imm;
npc = pc_in;
always_comb begin
case(addr_mode)
PC:
case (branch_taken)
1'b0: begin
branch_addr = pc_in + imm;
npc = pc_in;
end
1'b1: begin
branch_addr = pc_in + imm;
npc = branch_addr;
end
endcase
RD:
case (branch_taken)
1'b0: begin
branch_addr = imm + rs1d;
npc = pc_in;
end
1'b1: begin
branch_addr = imm + rs1d;
npc = branch_addr;
end
endcase
default: begin
branch_addr = pc_in + imm;
npc = pc_in;
end
1'b1: begin
branch_addr = pc_in + imm;
npc = branch_addr;
end
endcase
RD:
case (branch_taken)
1'b0: begin
branch_addr = imm + rs1d;
npc = pc_in;
end
1'b1: begin
branch_addr = imm + rs1d;
npc = branch_addr;
end
endcase
default: begin
branch_addr = pc_in + imm;
npc = pc_in;
end
endcase
end
end

endmodule
endmodule
26 changes: 13 additions & 13 deletions rtl/Branch_Eval.sv
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@@ -1,28 +1,28 @@

//Branch condition definitions
parameter NE = 2'h0; //Non branching instruction
parameter ALU = 2'h1; //Branch condition is < or !=
parameter NALU = 2'h2; //Branch condition is >= or =
parameter AL = 2'h3; //Jump instruction
parameter NE = 2'h0; //Non branching instruction
parameter ALU = 2'h1; //Branch condition is < or !=
parameter NALU = 2'h2; //Branch condition is >= or =
parameter AL = 2'h3; //Jump instruction



module Branch_Eval #(
WordSize = 32
) (
WordSize = 32
)(
input [WordSize - 1:0] alu_out,
input [1:0] branch_cond,
output logic act_taken
);

always_comb begin
case (branch_cond)
NE: act_taken = 0;
ALU: act_taken = |alu_out;
NALU: act_taken = ~(|alu_out);
AL: act_taken = 1;
always_comb begin
case(branch_cond)
NE: act_taken = 0;
ALU: act_taken = |alu_out;
NALU: act_taken = ~(|alu_out);
AL: act_taken = 1;
endcase
end
end


endmodule
41 changes: 19 additions & 22 deletions rtl/Branch_Manager.sv
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@@ -1,39 +1,36 @@
module Branch_Manager #(
WordSize = 32
) (
input clk,
input rstn,
input pred_taken,
input act_taken,
input [WordSize - 1:0] pred_pc,
input [WordSize - 1:0] pred_addr,
WordSize = 32
)(
input clk, rstn, pred_taken, act_taken,
input [WordSize - 1:0] pred_pc, pred_addr,
output logic flush,
output logic [WordSize - 1:0] npc
);

logic restart;
logic restart;

always_ff @(posedge clk or negedge rstn) begin
always @ (posedge clk or negedge rstn) begin
if (!rstn) begin
restart <= 1;
flush <= 0;
npc <= 0;
end else begin
restart <= 0;

end
else begin
if ((pred_taken != act_taken) && !restart) begin
flush <= 1;
case (act_taken)
0: npc <= pred_pc + 4;
1: npc <= pred_addr;
case(act_taken)
0: npc <= pred_pc + 4;
1: npc <= pred_addr;
endcase
end else begin
end
else begin
flush <= 0;
case (pred_taken)
0: npc <= pred_pc + 4;
1: npc <= pred_addr;
case(pred_taken)
0: npc <= pred_pc + 4;
1: npc <= pred_addr;
endcase
end
if (restart) restart <= 0;
end
end
endmodule
end
endmodule
38 changes: 18 additions & 20 deletions rtl/Branch_Predictor.sv
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@@ -1,40 +1,38 @@
module Branch_Predictor (
input clk,
input rstn_h,
input act_taken,
input pred_taken,
input [1:0] branch_occr,
input [1:0] branch_cond,
input clk, rstn_h, act_taken, pred_taken,
input [1:0] branch_occr, branch_cond,
output logic branch_taken
);
logic curr_pred, incorrect_pred;
logic curr_pred, incorrect_pred;

always_ff @(posedge clk or negedge rstn_h) begin
always @ (posedge clk or negedge rstn_h) begin
if (!rstn_h) begin
curr_pred <= 0;
incorrect_pred <= 0;
end else begin
end
else begin
if (^branch_cond == 0) begin
curr_pred <= curr_pred;
incorrect_pred <= incorrect_pred;
end else if (act_taken ^ pred_taken == 0) begin
end
else if (act_taken ^ pred_taken == 0) begin
curr_pred <= curr_pred;
incorrect_pred <= 0;
end else if (incorrect_pred) begin
end
else if (incorrect_pred) begin
curr_pred <= ~curr_pred;
incorrect_pred <= 1;
end else begin
end
else begin
curr_pred <= curr_pred;
incorrect_pred <= 1;
end
end
end

always_comb begin
case (branch_occr[1])
0: branch_taken = branch_occr[0];
1: branch_taken = curr_pred;
end
always_comb begin
case(branch_occr[1])
0: branch_taken = branch_occr[0];
1: branch_taken = curr_pred;
endcase
end

end
endmodule
64 changes: 15 additions & 49 deletions rtl/Con_EX.sv
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@@ -1,54 +1,20 @@
module Con_EX #(
WordSize = 32
) (
input clk,
input rstn,
input branch_taken_in,
input [1:0] a_sel,
input [1:0] b_sel,
input [WordSize - 1:0] imm,
input [WordSize - 1:0] pc_in,
input [WordSize - 1:0] rs1d,
input [WordSize - 1:0] rs2d_in,
input [WordSize - 1:0] branch_addr_in,
input [4:0] rdn_in,
input [5:0] alu_mode,
output logic branch_taken,
output logic [4:0] rdn,
output logic [WordSize - 1:0] pc,
output logic [WordSize - 1:0] branch_addr,
output logic [WordSize - 1:0] rs2d,
output logic [WordSize - 1:0] alu_out
WordSize = 32
)(
input clk, rstn, branch_taken_in,
input[1:0] a_sel, b_sel,
input[WordSize - 1:0] imm, pc_in, rs1d, rs2d_in, branch_addr_in,
input[4:0] rdn_in,
input[5:0] alu_mode,
output logic branch_taken,
output logic [4:0] rdn,
output logic [WordSize - 1:0] pc, branch_addr, rs2d, alu_out
);

logic [WordSize - 1:0] a, b;

logic [WordSize - 1:0] a, b;
IDEX #(WordSize) id_ex_latch(.clk(clk), .rstn(rstn), .branch_taken_in(branch_taken_in), .a_sel(a_sel), .b_sel(b_sel), .imm(imm), .pc_in(pc_in), .rs1d(rs1d), .rs2d_in(rs2d_in), .branch_addr_in(branch_addr_in), .rdn_in(rdn_in), .branch_taken(branch_taken), .rdn(rdn), .pc(pc), .branch_addr(branch_addr), .rs2d(rs2d), .a(a), .b(b));

IDEX #(WordSize) id_ex_latch (
.clk(clk),
.rstn(rstn),
.branch_taken_in(branch_taken_in),
.a_sel(a_sel),
.b_sel(b_sel),
.imm(imm),
.pc_in(pc_in),
.rs1d(rs1d),
.rs2d_in(rs2d_in),
.branch_addr_in(branch_addr_in),
.rdn_in(rdn_in),
.branch_taken(branch_taken),
.rdn(rdn),
.pc(pc),
.branch_addr(branch_addr),
.rs2d(rs2d),
.a(a),
.b(b)
);
Alu #(WordSize) alu_modulemake(.a(a), .b(b), .alu_mode(alu_mode), .alu_out(alu_out));

Alu #(WordSize) alu_modulemake (
.a(a),
.b(b),
.alu_mode(alu_mode),
.alu_out(alu_out)
);

endmodule
endmodule
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