refactor: Formatting and syntax fixes

[nickelpro]

This PR is a courtesy because it will break outstanding work that will need to be rebased. This will merge in a day or two if there's no other issues.

Build:

• Update vcpkg bootstrapping to new style
• Inline vcpkg-configuration.json
• Update baselines

Style:

• Reformat all SystemVerilog files with verible-format, might add this to the component template to be enforced always
• or -> ,

Function:

• Fix all verilog-style always blocks -> SV-style always_ff blocks
• Fix all blocking assignments in non-blocking contexts
• Fix a couple missing semi-colons
• Normalize all port lists, necessary for some synthesizers (Quartus) ((and also just good practice))

Refactor:

• Significantly simplify Alu.sv, don't try to out-smart the synthesizer (this isn't comp arch, if you want a less-than you can just use less-than)
• Avoid unnecessary clock-gate latch in Branch_Manager.sv

[codecov]

Codecov Report

Attention: 4 lines in your changes are missing coverage. Please review.

Comparison is base (e74b8c0) 97.86% compared to head (44066ae) 98.18%.

Files	Patch %	Lines
rtl/Branch_Predictor.sv	87.50%	2 Missing ⚠️
rtl/IDEX.sv	95.65%	1 Missing ⚠️
rtl/Pipeline_Reset.sv	92.30%	1 Missing ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main     #147      +/-   ##
==========================================
+ Coverage   97.86%   98.18%   +0.32%     
==========================================
  Files          13       13              
  Lines         234      276      +42     
==========================================
+ Hits          229      271      +42     
  Misses          5        5              

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[nickelpro]

Also coverage is completely broken because of a bug in the way tests are done, that fix is coming in a separate PR