A survey on architectural simulators focused on CPU caches.

This is an implementation of a simple CPU in Logisim and Verilog.

Simple RISC-V CPUs running a baremental ray-tracer program.

Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.

16-Bit RISC Based CPU Design and Simulation in Python

CENOS: The Modern CPU Simulator

These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.

Logic gate & circuit simulation framework; 8-bit CPU simulation.

The project will simulate a simple computer system consisting of a CPU and Memory.

Simple TLB (Translation lookaside buffer) realization on verilog.

Simply the simulated version of the CPU based on 'Reptile' design. It takes an assembly code file as input and shows the final state of all registers and data memory.

A binary port of Tera

Intel8085-Simulator: An ongoing project to create a simulator for the Intel 8085 microprocessor. Users can run binary files containing Intel 8085 opcodes and observe their execution. Feel free to use this brief description as needed! 🚀

In this repo, I'll put projects that I've done in collaboration with chatbots like OpenAI ChatGPT, Google Bard, etc.

simulate cpu, memory and disk operations

6502 CPU simulator

An Assembly Language Parser and Evaluator written in Haskell using Parsec. Parses and executes assembly-like code, simulating a CPU with registers, flags, stack, and control flow instructions.

CPU Cache Simulation using gem5

Similar - Logic Design & Simulation