The NYU ProcDesign Core will be a RISCV-32I compatible core with a 5 stage pipeline.
The repo contains the modules and test for components that make up the core design.
The core modules include:
The branch logic modules include:
The pipeline will have 5 stages:
- Instruction Fetch (IF)
- Instuction Decode (ID)
- Execution (EX)
- Memory Access (MEM)
- Write Back (WB)
The pipeline will require 4 latch modules:
Control Modules:
Cache Modules:
- Instruction Cache Manager
- L1 Instruction Cache
- Data Cache Manager
- L1 Data Cache
- L2 Data Cache
- L3 Data Cache