A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Designing means to communicate as an SPI master, being a part of AXI interface

An open-source HDL register code generator fast enough to run in real time.

Slaves for AXI-lite interface

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

🏄 Custom IP for vector operations

This is a collection of some examples designed in the Vivado Design Suite.

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

Registers bank with Axi-Lite interface

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite